Added explicit rst input to RAM and PC as well as the MIPS processor.

modules/ram.sv

@@ -2,7 +2,7 @@
 `define RAM_H
 
 module ram #(addrwidth=9, datawidth=5)(
-    input logic [0:0] clk,
+    input logic [0:0] clk, input logic [0:0] rst,
     input logic [addrwidth-1:0] addr,
     input logic [0:0] we,
     input logic [datawidth-1:0] data_in,
@@ -12,15 +12,12 @@ module ram #(addrwidth=9, datawidth=5)(
     // TODO: Make this byte-sized, NOT word-sized!
     logic [2**datawidth-1:0] mem[0:255];
 
-    // NOTE: Possible issue with assignments still pending by end of initial block
-    initial begin
-        for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
-            mem[ADDR] <= 32'b0;
-        end
-    end
-
     always_ff @(posedge clk) begin
-        if (we) begin
+        if (rst) begin
+            for (integer ADDR = 0; ADDR < 256; ADDR = ADDR + 1) begin
+                mem[ADDR] <= 32'b0;
+            end
+        end else if (we) begin
             mem[addr] <= data_in;
         end
     end