TroubleElectrical/FPGA_Uni
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Added explicit rst input to RAM and PC as well as the MIPS processor.

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riley committed 2026-10-16 12:11:19 +11:00
1 parent c717bf189c
commit e7fff9f3dc
4 files changed
+24 -21
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modules/assignment2.sv
+3 -3
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@@ -13,7 +13,7 @@
module assignment2 #(width=5, ramsz=9, romsz=10) (
input logic [0:0] clk
input logic [0:0] clk, input logic [0:0] rst
`ifdef QUARTUS_SYNTH
,
input logic [4:0] HID_Register,
@@ -56,12 +56,12 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
logic [2**width-1:0] rd_alu;
logic [2**width-1:0] rt_alu;
instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
rom #(romsz, width) ROM (pc_addr, instruction);
logic [2**width-1:0] rd_mem;
ram #(ramsz, width) RAM (clk, rd_alu, M2W, rt, rd_mem);
ram #(ramsz, width) RAM (clk, rst, rd_alu, M2W, rt, rd_mem);
control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW