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Updated assignment3 instruction counter code to be more consistent with other modules

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riley committed 2026-11-05 15:46:05 +11:00
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commit de1f346f64
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modules/assignment3.sv
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@@ -18,19 +18,18 @@ module assignment3 #(width=5, romsz=9, ramsz=10)(
logic [31:0] regs_out [32]; logic [31:0] regs_out [32];
logic [2**width-1:0] pc_addr, pc_addr_2; logic [2**width-1:0] pc_addr, pc_addr_1, pc_addr_2;
logic [2**width-1:0] pc_addr_write; logic [2**width-1:0] pc_addr_write;
logic [0:0] pc_we; logic [0:0] pc_we;
// TODO: Verify if we need a clk gating on pc_addr // TODO: Verify if we need a clk gating on pc_addr
instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr); instruction_counter #(width) PC (clk, rst, pc_we, pc_addr_write, pc_addr);
gatereg #(width, 2) gate_pc_addr_1(clk, rst, 1'b1, pc_addr, pc_addr_2); gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, pc_addr_1);
gatereg #(width, 1) gate_pc_addr_1(clk, rst, 1'b1, pc_addr_1, pc_addr_2);
logic [2**width-1:0] rom_rd; logic [2**width-1:0] rom_rd;
logic [2**width-1:0] rom_addr;
logic [2**width-1:0] instruction, instruction_1; logic [2**width-1:0] instruction, instruction_1;
rom #("./asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex", romsz, width) ROM (rom_addr[romsz-1:0], rom_rd); rom #("./asm/bin/ELEC4720-2026s2-Ass-03-NoHazardsDemo.hex", romsz, width) ROM (pc_addr_1[romsz-1:0], rom_rd);
gatereg #(width, 1) gate_pc_addr(clk, rst, 1'b1, pc_addr, rom_addr);
gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction); gatereg #(width, 1) gate_instruction(clk, rst, 1'b1, rom_rd, instruction);
gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1); gatereg #(width, 1) gate_instruction_1(clk, rst, 1'b1, instruction, instruction_1);