Added files into modelsim folder
This commit is contained in:
14 files changed
+436
-13
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@@ -0,0 +1,14 @@
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`include "rom.sv"
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module ByteIM #(parameter m=5,n=2) (
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input logic [m-1:0] Ad,
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output logic [(2**n)*8-1:0] Dout );
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// 2**n byte wide words
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// m bit wide byte address
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// 2**m bytes of memory
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// 2**(m-n) memory words
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// 2**(n+3) bit wide words
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// Reads the whole word that contains the addressed byte
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ROM #(m-n,2**(n+3)) wordrom(Ad[m-1:n],Dout)
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endmodule
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+7
-4
@@ -8,11 +8,13 @@
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// flags[1:1] = Overflow
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module alu #(parameter width=2)(input logic [3:0] op,
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input logic [2**width-1:0] A, input logic [2**width-1:0] B,
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output logic [2**width-1:0] OUT_1, output logic[1:0] flags);
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output logic [2**width-1:0] OUT_1, output logic[2:0] flags
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);
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// intermediate logic for handling asu output
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logic [0:0] asu_op;
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logic [2**width-1:0] asu_out;
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logic [1:0] asu_flags;
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logic [2:0] asu_flags;
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asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
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logic [2**width-1:0] lu_out;
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@@ -32,6 +34,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
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4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
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default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
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endcase
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asu_flags[2] = OUT_1 == 0;
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end
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endmodule
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`endif
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`endif
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@@ -0,0 +1,107 @@
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`ifndef ASS_2_SV
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`define ASS_2_SV
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`include "rom.sv"
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`include "ram.sv"
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`include "register_file.sv"
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`include "instruction_counter.sv"
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`include "control_unit.sv"
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`include "alu.sv"
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`include "shifter.sv"
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`include "sign_extender.sv"
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`include "seven_seg_4digit.sv"
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module assignment2 #(width=5, ramsz=9, romsz=10) (
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input logic [0:0] clk
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`ifdef QUARTUS_SYNTH
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,
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input logic [4:0] HID_Register,
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input logic [0:0] HID_PC,
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input logic [0:0] HID_Hi_Low,
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output logic[7:0] out_seg_0,
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output logic[7:0] out_seg_1,
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output logic[7:0] out_seg_2,
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output logic[7:0] out_seg_3
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`endif
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);
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// Intermediate for displaying high / low of PC or Register
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logic[15:0] PC_Reg_Display;
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// Program / Instruction Counter Intermediates
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logic [romsz-1:0] pc_addr;
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logic [romsz-1:0] pc_addr_write;
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logic [0:0] pc_we;
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logic [2**width-1:0] instruction;
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// Instruction Classifier Intermediates
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logic [0:0] M2R;
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logic [0:0] M2W;
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logic [0:0] B;
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logic [3:0] ALU_FN;
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logic [0:0] ALU_SRC;
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logic [0:0] RDST;
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logic [0:0] RW;
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// Register File intermediates
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logic [2:0] flags;
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logic [2**width-1:0] rs;
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logic [2**width-1:0] rt;
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logic [2**width-1:0] rd;
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logic [0:0] rd_we;
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logic [31:0] regs_out [32];
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instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
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rom #(romsz, 2**width) ROM (pc_addr, instruction);
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logic [2**width-1:0] rd_mem;
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ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
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control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
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M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
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);
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register_file #(width, 5) REGS (
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clk, rd_we,
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instruction[20:16], rd,
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(RDST) ? instruction[15:11] : instruction[20:16], rt,
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instruction[25:21], rs,
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regs_out
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);
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// Always use sign-extension
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logic [2**width-1:0] rt_imm;
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sign_extender #(4, width) SIGNEXT(1'b1, instruction[15:0], rt_imm);
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// TODO:
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// - ALU srcB
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// - PCBranch (rel jump of 4-byte words)
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logic [2**width-1:0] rd_alu;
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logic [2**width-1:0] rt_alu;
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alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
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assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
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assign pc_we = B & flags[2];
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assign pc_addr_write = (rt_imm << 2) + pc_addr;
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assign rd_we = RW;
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assign rd = (M2R) ? rd_alu : rd_mem;
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// Temporary Test output
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// assign PC_Reg_Display = 16'hC342;
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assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
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seven_seg_4digit display (
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.num(PC_Reg_Display),
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.segments0(out_seg_0),
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.segments1(out_seg_1),
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.segments2(out_seg_2),
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.segments3(out_seg_3)
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);
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endmodule
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`endif
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+5
-2
@@ -4,9 +4,11 @@
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module asu #(parameter width = 2)(
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input logic [0:0] op,
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input logic[2**width-1:0] A, input logic[2**width-1:0] B,
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output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
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output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
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);
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logic [2**width-1:0] operand;
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always_comb begin
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// A + (sub) ? B : -B
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// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
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@@ -18,5 +20,6 @@ module asu #(parameter width = 2)(
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// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
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// Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
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assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
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endmodule
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`endif
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`endif
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@@ -0,0 +1,36 @@
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`ifndef CONTROL_UNIT_H
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`define CONTROL_UNIT_H
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`include "instruction_classifier.sv"
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module control_unit (
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input logic [5:0] op, input logic [5:0] func,
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output logic [0:0] M2R, // Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
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output logic [0:0] M2W, // Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
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output logic [0:0] B, // AND'ed with flags to determine if branch is permitted
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output logic [3:0] ALU_FN, // Controls what function the ALU is to perform
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output logic [0:0] ALU_SRC, // Controls whether to use the rt/B register read port or 16-bit immediate
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output logic [0:0] RDST, // Controls where to look in the instruction encoding for the register write address
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output logic [0:0] RW // Enable register write port
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);
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logic [0:0] TYPE_R;
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logic [0:0] TYPE_B1;
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logic [0:0] TYPE_J;
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logic [0:0] TYPE_B2;
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logic [0:0] TYPE_I;
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logic [0:0] TYPE_F;
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logic [0:0] TYPE_M;
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instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
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always_comb begin
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M2R = TYPE_M & op[3];
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M2W = TYPE_M & ~op[3];
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B = TYPE_B1 | TYPE_B2 | TYPE_J;
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ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
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ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
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RDST = TYPE_I; // Imm ops store back into rt
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RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
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end
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endmodule
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`endif
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@@ -0,0 +1,21 @@
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`ifndef INSTRUCTION_COUNTER_H
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`define INSTRUCTION_COUNTER_H
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module instruction_counter #(parameter width=5)(
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input logic [0:0] clk, input logic [0:0] we,
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input logic [2**width-1:0] W,
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output logic [2**width-1:0] addr
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);
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logic [2**width-1:0] pc;
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always_ff @(posedge clk) begin
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if (we) begin
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pc <= W;
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end else begin
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pc <= pc + 4;
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end
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end
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assign addr = pc;
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endmodule
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`endif
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+4
-4
@@ -1,13 +1,13 @@
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`ifndef LU_H_SV
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`define LU_H_SV
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module lu #(parameter width = 2) (
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input logic [1:0] op,
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input logic [2**width-1:0] A,
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input logic [1:0] op, // 2 bit operand
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input logic [2**width-1:0] A, // width defined as 2^n
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input logic [2**width-1:0] B,
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output logic [2**width-1:0] Y);
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always_comb begin
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case (op)
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case (op) // different operations of A and B based on operand
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2'b00: Y = A & B;
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2'b01: Y = A | B;
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2'b10: Y = A ^ B;
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@@ -16,4 +16,4 @@ module lu #(parameter width = 2) (
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endcase
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end
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endmodule
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`endif
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`endif
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@@ -0,0 +1,95 @@
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`include "assignment2.sv"
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`define PRINT_REGISTERS(regs)\
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$display("\tt0-t8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n\ts0-s8: \t0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",\
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regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15], \
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regs[16], regs[17], regs[18], regs[19], regs[20], regs[21], regs[22], regs[23] \
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);
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`define TEST_CHECK(cond) if (cond) begin end else begin \
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$display("Check %s failed\n", `"cond`"); \
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`PRINT_REGISTERS(CPU.REGS.regs); \
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num_errors += 1; \
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end
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module mips_tb(input logic [0:0] clk);
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assignment2 #(5) CPU (clk);
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integer num_errors = 0;
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initial begin
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// Zero out lower registers
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$display("Beginning MIPS tests");
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assign num_errors = 0;
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for (integer N = 1; N < 32; ++N)
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CPU.REGS.regs[N] = 32'd0;
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// Check R-type / initialise
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#1;
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`TEST_CHECK(CPU.REGS.regs[8] == 32'd0);
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#1;
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`TEST_CHECK(CPU.REGS.regs[9] == (CPU.REGS.regs[8] + 32'd7));
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// Check load-store
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#1;
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`TEST_CHECK(CPU.RAM.mem[0] == CPU.REGS.regs[9]);
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#1;
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`TEST_CHECK(CPU.REGS.regs[10] == CPU.RAM.mem[0]);
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// Check arithmetic
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#1;
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`TEST_CHECK(CPU.REGS.regs[11] == (CPU.REGS.regs[9] + CPU.REGS.regs[10]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[12] == (CPU.REGS.regs[9] - CPU.REGS.regs[11]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[13] == (CPU.REGS.regs[9] + 3));
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#1;
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`TEST_CHECK(CPU.REGS.regs[14] == (CPU.REGS.regs[12] + CPU.REGS.regs[13]));
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// Check logic instructions
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#1;
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`TEST_CHECK(CPU.REGS.regs[16] == (CPU.REGS.regs[9] & CPU.REGS.regs[13]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[17] == (CPU.REGS.regs[9] | CPU.REGS.regs[13]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[18] == (CPU.REGS.regs[9] ^ CPU.REGS.regs[13]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[19] == ( ~(CPU.REGS.regs[9] | CPU.REGS.regs[13]) ));
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// Check SLT instructions
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#1;
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`TEST_CHECK(CPU.REGS.regs[20] == $signed(CPU.REGS.regs[12]) < $signed(CPU.REGS.regs[14]));
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#1;
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`TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
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// Check loop branching
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for (integer N = 1; N < 11; ++N) begin
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#1;
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`TEST_CHECK(CPU.REGS.regs[0] == 32'(N));
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#1;
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`TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
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end
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// Final state check
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#1;
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`TEST_CHECK(CPU.REGS.regs[8] == 32'd10);
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`TEST_CHECK(CPU.REGS.regs[9] == 32'd7);
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`TEST_CHECK(CPU.REGS.regs[10] == 32'd7);
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`TEST_CHECK(CPU.REGS.regs[11] == 32'd14);
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`TEST_CHECK(CPU.REGS.regs[12] == -32'sd7);
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`TEST_CHECK(CPU.REGS.regs[13] == 32'd10);
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`TEST_CHECK(CPU.REGS.regs[14] == 32'd3);
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`TEST_CHECK(CPU.REGS.regs[15] == 32'd0);
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`TEST_CHECK(CPU.REGS.regs[16] == 32'd2);
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`TEST_CHECK(CPU.REGS.regs[17] == 32'd15);
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`TEST_CHECK(CPU.REGS.regs[18] == 32'd13);
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`TEST_CHECK(CPU.REGS.regs[19] == -32'sd16);
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`TEST_CHECK(CPU.REGS.regs[20] == 32'd1);
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`TEST_CHECK(CPU.REGS.regs[21] == 32'd0);
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`TEST_CHECK(CPU.REGS.regs[22] == 32'd0);
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`TEST_CHECK(CPU.REGS.regs[23] == 32'd0);
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if (num_errors == 0) $display("\x1b[38;5;10mAll MIPS tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d MIPS test(s) failing\x1b[m", num_errors);
|
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end
|
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endmodule
|
||||
@@ -0,0 +1,31 @@
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`ifndef RAM_H
|
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`define RAM_H
|
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module ram #(addrwidth=9, datawidth=5)(
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input logic [0:0] clk,
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input logic [2**addrwidth-1:0] addr,
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||||
input logic [0:0] we,
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input logic [datawidth-1:0] data_in,
|
||||
output logic [datawidth-1:0] data_out
|
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);
|
||||
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// TODO: Make this byte-sized, NOT word-sized!
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logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
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// NOTE: Possible issue with assignments still pending by end of initial block
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initial begin
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for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
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mem[ADDR] <= 8'b0;
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end
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end
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always_ff @(posedge clk) begin
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||||
if (we) begin
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mem[addr] <= data_in;
|
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end
|
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end
|
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assign data_out = mem[addr];
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|
||||
endmodule
|
||||
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`endif
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@@ -0,0 +1,28 @@
|
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`ifndef REGISTER_FILE_H
|
||||
`define REGISTER_FILE_H
|
||||
|
||||
module register_file #(parameter width=5, parameter nregs=5)(
|
||||
input logic [0:0] clk, input logic[0:0] we,
|
||||
input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
|
||||
input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
|
||||
input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2,
|
||||
output logic [2**width-1:0] regs_out [2**nregs]
|
||||
);
|
||||
localparam BW = 2**width;
|
||||
logic [2**width-1:0] regs[2**nregs];
|
||||
|
||||
initial begin
|
||||
regs[0] = {(2**width){1'b0}};
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (we & (WA != {(2**width){1'b0}} )) begin
|
||||
regs[WA] <= WD;
|
||||
end
|
||||
end
|
||||
|
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assign RD1 = regs[RA1];
|
||||
assign RD2 = regs[RA2];
|
||||
assign regs_out = regs; // Expose registers externally
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,24 @@
|
||||
`ifndef ROM_H
|
||||
`define ROM_H
|
||||
|
||||
module rom #(parameter m=7,p=4) (
|
||||
input logic [m-1:0] Ad,
|
||||
output logic [p-1:0] Dout
|
||||
);
|
||||
|
||||
logic [p-1:0] mem[2**m-1:0];
|
||||
assign Dout = mem[Ad];
|
||||
|
||||
//Load the program in memory
|
||||
// The machine code stored in text file program.dat written in Hex format
|
||||
initial begin
|
||||
`ifdef QUARTUS_SYNTH
|
||||
$readmemh("../../asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
`else
|
||||
$readmemh("./asm/bin/ELEC4720-2026s2-Ass-02-Demo.txt",mem); //$readmemb for binary
|
||||
`endif
|
||||
end
|
||||
endmodule // end rom module
|
||||
|
||||
`endif
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
`ifndef SEVEN_SEG_4_H_SV
|
||||
`define SEVEN_SEG_4_H_SV
|
||||
|
||||
`include "seven_seg.sv"
|
||||
module seven_seg_4digit (
|
||||
input logic [15:0] num,
|
||||
output logic [7:0] segments0,
|
||||
output logic [7:0] segments1,
|
||||
output logic [7:0] segments2,
|
||||
output logic [7:0] segments3
|
||||
);
|
||||
|
||||
// Rightmost digit
|
||||
seven_seg digit0 (
|
||||
.num(num[3:0]),
|
||||
.rbi_inv(1'b0),
|
||||
.segments(segments0)
|
||||
);
|
||||
|
||||
// Second digit from right
|
||||
seven_seg digit1 (
|
||||
.num(num[7:4]),
|
||||
.rbi_inv(1'b0),
|
||||
.segments(segments1)
|
||||
);
|
||||
|
||||
// Third digit from right
|
||||
seven_seg digit2 (
|
||||
.num(num[11:8]),
|
||||
.rbi_inv(1'b0),
|
||||
.segments(segments2)
|
||||
);
|
||||
|
||||
// Leftmost digit
|
||||
seven_seg digit3 (
|
||||
.num(num[15:12]),
|
||||
.rbi_inv(1'b0),
|
||||
.segments(segments3)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
|
||||
+3
-3
@@ -1,9 +1,9 @@
|
||||
`ifndef SHIFTER_H_SV
|
||||
`define SHIFTER_H_SV
|
||||
module shifter #(width=2)(input logic [2:0] op,
|
||||
input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
|
||||
input logic[2**width-1:0] A, input logic[2**width-1:0] B, input logic[width-1:0] C,
|
||||
output logic[2**width-1:0] OUT_1);
|
||||
|
||||
// A and B are 2^n bits wide and C is n bits wide as according to the docs
|
||||
always_comb begin
|
||||
case (op)
|
||||
3'b000: OUT_1 = A << C;
|
||||
@@ -16,4 +16,4 @@ module shifter #(width=2)(input logic [2:0] op,
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
`endif
|
||||
`endif
|
||||
@@ -0,0 +1,17 @@
|
||||
`ifndef SIGN_EXTENDER_H
|
||||
`define SIGN_EXTENDER_H
|
||||
|
||||
module sign_extender #(in_width=4, out_width=5)(
|
||||
input logic [0:0] op,
|
||||
input logic [2**in_width-1:0] val,
|
||||
output logic [2**out_width-1:0] ext_val
|
||||
);
|
||||
always_comb begin
|
||||
if (op) begin
|
||||
ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
|
||||
end else begin
|
||||
ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
`endif
|
||||
Reference in new issue
Block a user