Added files into modelsim folder

ModelSim/ram.sv

@@ -0,0 +1,31 @@
+`ifndef RAM_H
+`define RAM_H
+
+module ram #(addrwidth=9, datawidth=5)(
+    input logic [0:0] clk,
+    input logic [2**addrwidth-1:0] addr,
+    input logic [0:0] we,
+    input logic [datawidth-1:0] data_in,
+    output logic [datawidth-1:0] data_out
+);
+
+    // TODO: Make this byte-sized, NOT word-sized!
+    logic [2**datawidth-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+
+    // NOTE: Possible issue with assignments still pending by end of initial block
+    initial begin
+        for (integer ADDR = 0; ADDR < 2**(addrwidth+$clog2(datawidth)-3); ++ADDR) begin
+            mem[ADDR] <= 8'b0;
+        end
+    end
+
+    always_ff @(posedge clk) begin
+        if (we) begin
+            mem[addr] <= data_in;
+        end
+    end
+    assign data_out = mem[addr];
+
+endmodule
+
+`endif