Added files into modelsim folder

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TroubleElectrical committed 2026-10-16 10:10:37 +11:00
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commit dca673b039
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@@ -1,13 +1,13 @@
`ifndef LU_H_SV
`define LU_H_SV
module lu #(parameter width = 2) (
input logic [1:0] op,
input logic [2**width-1:0] A,
input logic [1:0] op, // 2 bit operand
input logic [2**width-1:0] A, // width defined as 2^n
input logic [2**width-1:0] B,
output logic [2**width-1:0] Y);
always_comb begin
case (op)
case (op) // different operations of A and B based on operand
2'b00: Y = A & B;
2'b01: Y = A | B;
2'b10: Y = A ^ B;
@@ -16,4 +16,4 @@ module lu #(parameter width = 2) (
endcase
end
endmodule
`endif
`endif