Added files into modelsim folder

ModelSim/control_unit.sv

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+`ifndef CONTROL_UNIT_H
+`define CONTROL_UNIT_H
+`include "instruction_classifier.sv"
+
+module control_unit (
+    input logic [5:0] op, input logic [5:0] func,
+    output logic [0:0] M2R,     //  Enables writing data stored in memory at the address (rs/A)+(ALU_SRC ? imm : rt/B) into rd
+    output logic [0:0] M2W,     //  Enable writing data stored in rt/B into memory at the address (rs/A)+(ALU_SRC ? imm : rt/B)
+    output logic [0:0] B,       //  AND'ed with flags to determine if branch is permitted
+    output logic [3:0] ALU_FN,  //  Controls what function the ALU is to perform
+    output logic [0:0] ALU_SRC, //  Controls whether to use the rt/B register read port or 16-bit immediate 
+    output logic [0:0] RDST,    //  Controls where to look in the instruction encoding for the register write address
+    output logic [0:0] RW       //  Enable register write port
+);
+    logic [0:0] TYPE_R;
+    logic [0:0] TYPE_B1;
+    logic [0:0] TYPE_J;
+    logic [0:0] TYPE_B2;
+    logic [0:0] TYPE_I;
+    logic [0:0] TYPE_F;
+    logic [0:0] TYPE_M;
+
+    instruction_classifier CLASSIFIER (op, TYPE_R, TYPE_B1, TYPE_J, TYPE_B2, TYPE_I, TYPE_F, TYPE_M);
+
+    always_comb begin
+        M2R = TYPE_M & op[3];
+        M2W = TYPE_M & ~op[3];
+        B = TYPE_B1 | TYPE_B2 | TYPE_J;
+        ALU_FN = (func & {(6){TYPE_R}}) | ( {4'b0000, op[1:0]} & {(6){TYPE_I}});
+        ALU_SRC = TYPE_B1 | TYPE_B2 | TYPE_I | TYPE_M;
+        RDST = TYPE_I;  // Imm ops store back into rt
+        RW = TYPE_R | TYPE_I | (TYPE_M & op[3]); // All ALU R-type ops, Addi/Addiu ops, and memory loads
+    end
+
+endmodule
+`endif