Added files into modelsim folder

ModelSim/asu.sv

@@ -4,9 +4,11 @@
 module asu #(parameter width = 2)(
 	input logic [0:0] op,
 	input logic[2**width-1:0] A, input logic[2**width-1:0] B,
-   output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN);
+    output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
+    );
 
     logic [2**width-1:0] operand;
+
     always_comb begin
         // A + (sub) ? B : -B
         // Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
@@ -18,5 +20,6 @@ module asu #(parameter width = 2)(
     // Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
     // Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
     assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
+
 endmodule
-`endif
+`endif