Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
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// Copyright (C) 2025 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, the Altera Quartus Prime License Agreement,
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// the Altera IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Altera and sold by Altera or its authorized distributors. Please
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// refer to the Altera Software License Subscription Agreements
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// on the Quartus Prime software download page.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition"
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// DATE "09/09/2026 14:23:06"
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//
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// Device: Altera 5CGXFC5C6F27C7 Package FBGA672
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//
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//
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// This Verilog file should be used for Questa Altera FPGA (SystemVerilog) only
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//
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`timescale 1 ps/ 1 ps
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module alu (
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op,
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A,
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B,
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OUT_1,
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flags);
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input logic [3:0] op ;
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input logic [3:0] A ;
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input logic [3:0] B ;
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output logic [3:0] OUT_1 ;
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output logic flags [1:0];
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// Design Ports Information
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// op[0] => Location: PIN_H9, I/O Standard: 2.5 V, Current Strength: Default
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// op[1] => Location: PIN_B24, I/O Standard: 2.5 V, Current Strength: Default
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// op[2] => Location: PIN_K24, I/O Standard: 2.5 V, Current Strength: Default
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// op[3] => Location: PIN_V25, I/O Standard: 2.5 V, Current Strength: Default
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// A[0] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default
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// A[1] => Location: PIN_AF21, I/O Standard: 2.5 V, Current Strength: Default
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// A[2] => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default
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// A[3] => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default
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// B[0] => Location: PIN_C19, I/O Standard: 2.5 V, Current Strength: Default
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// B[1] => Location: PIN_T13, I/O Standard: 2.5 V, Current Strength: Default
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// B[2] => Location: PIN_B20, I/O Standard: 2.5 V, Current Strength: Default
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// B[3] => Location: PIN_E26, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[1] => Location: PIN_AA7, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[2] => Location: PIN_AF16, I/O Standard: 2.5 V, Current Strength: Default
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// OUT_1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default
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// flags[0] => Location: PIN_F12, I/O Standard: 2.5 V, Current Strength: Default
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// flags[1] => Location: PIN_W25, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \op[0]~input_o ;
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wire \op[1]~input_o ;
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wire \op[2]~input_o ;
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wire \op[3]~input_o ;
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wire \A[0]~input_o ;
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wire \A[1]~input_o ;
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wire \A[2]~input_o ;
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wire \A[3]~input_o ;
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wire \B[0]~input_o ;
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wire \B[1]~input_o ;
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wire \B[2]~input_o ;
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wire \B[3]~input_o ;
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wire \~QUARTUS_CREATED_GND~I_combout ;
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// Location: IOOBUF_X21_Y61_N36
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cyclonev_io_obuf \OUT_1[0]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[0]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[0]~output .bus_hold = "false";
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defparam \OUT_1[0]~output .open_drain_output = "false";
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defparam \OUT_1[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X6_Y0_N53
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cyclonev_io_obuf \OUT_1[1]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[1]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[1]~output .bus_hold = "false";
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defparam \OUT_1[1]~output .open_drain_output = "false";
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defparam \OUT_1[1]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X59_Y0_N19
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cyclonev_io_obuf \OUT_1[2]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[2]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[2]~output .bus_hold = "false";
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defparam \OUT_1[2]~output .open_drain_output = "false";
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defparam \OUT_1[2]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X40_Y61_N93
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cyclonev_io_obuf \OUT_1[3]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(OUT_1[3]),
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.obar());
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// synopsys translate_off
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defparam \OUT_1[3]~output .bus_hold = "false";
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defparam \OUT_1[3]~output .open_drain_output = "false";
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defparam \OUT_1[3]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X36_Y61_N19
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cyclonev_io_obuf \flags[0]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(flags[0]),
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.obar());
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// synopsys translate_off
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defparam \flags[0]~output .bus_hold = "false";
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defparam \flags[0]~output .open_drain_output = "false";
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defparam \flags[0]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOOBUF_X68_Y26_N39
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cyclonev_io_obuf \flags[1]~output (
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.i(gnd),
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.oe(vcc),
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.dynamicterminationcontrol(gnd),
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.seriesterminationcontrol(16'b0000000000000000),
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.parallelterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(flags[1]),
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.obar());
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// synopsys translate_off
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defparam \flags[1]~output .bus_hold = "false";
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defparam \flags[1]~output .open_drain_output = "false";
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defparam \flags[1]~output .shift_series_termination_control = "false";
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// synopsys translate_on
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// Location: IOIBUF_X19_Y61_N18
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cyclonev_io_ibuf \op[0]~input (
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.i(op[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[0]~input_o ));
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// synopsys translate_off
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defparam \op[0]~input .bus_hold = "false";
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defparam \op[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X65_Y61_N1
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cyclonev_io_ibuf \op[1]~input (
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.i(op[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[1]~input_o ));
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// synopsys translate_off
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defparam \op[1]~input .bus_hold = "false";
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defparam \op[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X68_Y41_N4
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cyclonev_io_ibuf \op[2]~input (
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.i(op[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[2]~input_o ));
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// synopsys translate_off
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defparam \op[2]~input .bus_hold = "false";
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defparam \op[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X68_Y19_N55
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cyclonev_io_ibuf \op[3]~input (
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.i(op[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\op[3]~input_o ));
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// synopsys translate_off
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defparam \op[3]~input .bus_hold = "false";
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defparam \op[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X68_Y12_N21
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cyclonev_io_ibuf \A[0]~input (
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.i(A[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[0]~input_o ));
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// synopsys translate_off
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defparam \A[0]~input .bus_hold = "false";
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defparam \A[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X51_Y0_N35
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cyclonev_io_ibuf \A[1]~input (
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.i(A[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[1]~input_o ));
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// synopsys translate_off
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defparam \A[1]~input .bus_hold = "false";
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defparam \A[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X51_Y0_N1
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cyclonev_io_ibuf \A[2]~input (
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.i(A[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[2]~input_o ));
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// synopsys translate_off
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defparam \A[2]~input .bus_hold = "false";
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defparam \A[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X62_Y0_N58
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cyclonev_io_ibuf \A[3]~input (
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.i(A[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\A[3]~input_o ));
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// synopsys translate_off
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defparam \A[3]~input .bus_hold = "false";
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defparam \A[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X59_Y61_N35
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cyclonev_io_ibuf \B[0]~input (
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.i(B[0]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[0]~input_o ));
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// synopsys translate_off
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defparam \B[0]~input .bus_hold = "false";
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defparam \B[0]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X15_Y0_N1
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cyclonev_io_ibuf \B[1]~input (
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.i(B[1]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[1]~input_o ));
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// synopsys translate_off
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defparam \B[1]~input .bus_hold = "false";
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defparam \B[1]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X62_Y61_N92
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cyclonev_io_ibuf \B[2]~input (
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.i(B[2]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[2]~input_o ));
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// synopsys translate_off
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defparam \B[2]~input .bus_hold = "false";
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defparam \B[2]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X68_Y37_N55
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cyclonev_io_ibuf \B[3]~input (
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.i(B[3]),
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.ibar(gnd),
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.dynamicterminationcontrol(gnd),
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.o(\B[3]~input_o ));
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// synopsys translate_off
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defparam \B[3]~input .bus_hold = "false";
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defparam \B[3]~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LABCELL_X46_Y55_N0
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cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
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// Equation(s):
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.dataa(gnd),
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.datab(gnd),
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.datac(gnd),
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.datad(gnd),
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.datae(gnd),
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.dataf(gnd),
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.datag(gnd),
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.cin(gnd),
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.sharein(gnd),
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.combout(\~QUARTUS_CREATED_GND~I_combout ),
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.sumout(),
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.cout(),
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.shareout());
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// synopsys translate_off
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defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
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defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
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defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
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// synopsys translate_on
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endmodule
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