Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)
This commit is contained in:
TroubleElectrical committed
1 parent
5acf1c8b87
commit
dc32347c9b
212 files changed
+8657
-71
No files matched your search
@@ -0,0 +1,477 @@
|
||||
Timing Analyzer report for alu
|
||||
Wed Sep 9 14:23:04 2026
|
||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Timing Analyzer Summary
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Slow 1100mV 85C Model Fmax Summary
|
||||
6. Timing Closure Recommendations
|
||||
7. Slow 1100mV 85C Model Setup Summary
|
||||
8. Slow 1100mV 85C Model Hold Summary
|
||||
9. Slow 1100mV 85C Model Recovery Summary
|
||||
10. Slow 1100mV 85C Model Removal Summary
|
||||
11. Slow 1100mV 85C Model Minimum Pulse Width Summary
|
||||
12. Slow 1100mV 85C Model Metastability Summary
|
||||
13. Slow 1100mV 0C Model Fmax Summary
|
||||
14. Slow 1100mV 0C Model Setup Summary
|
||||
15. Slow 1100mV 0C Model Hold Summary
|
||||
16. Slow 1100mV 0C Model Recovery Summary
|
||||
17. Slow 1100mV 0C Model Removal Summary
|
||||
18. Slow 1100mV 0C Model Minimum Pulse Width Summary
|
||||
19. Slow 1100mV 0C Model Metastability Summary
|
||||
20. Fast 1100mV 85C Model Setup Summary
|
||||
21. Fast 1100mV 85C Model Hold Summary
|
||||
22. Fast 1100mV 85C Model Recovery Summary
|
||||
23. Fast 1100mV 85C Model Removal Summary
|
||||
24. Fast 1100mV 85C Model Minimum Pulse Width Summary
|
||||
25. Fast 1100mV 85C Model Metastability Summary
|
||||
26. Fast 1100mV 0C Model Setup Summary
|
||||
27. Fast 1100mV 0C Model Hold Summary
|
||||
28. Fast 1100mV 0C Model Recovery Summary
|
||||
29. Fast 1100mV 0C Model Removal Summary
|
||||
30. Fast 1100mV 0C Model Minimum Pulse Width Summary
|
||||
31. Fast 1100mV 0C Model Metastability Summary
|
||||
32. Multicorner Timing Analysis Summary
|
||||
33. Board Trace Model Assignments
|
||||
34. Input Transition Times
|
||||
35. Signal Integrity Metrics (Slow 1100mv 0c Model)
|
||||
36. Signal Integrity Metrics (Slow 1100mv 85c Model)
|
||||
37. Signal Integrity Metrics (Fast 1100mv 0c Model)
|
||||
38. Signal Integrity Metrics (Fast 1100mv 85c Model)
|
||||
39. Clock Transfers
|
||||
40. Report TCCS
|
||||
41. Report RSKM
|
||||
42. Unconstrained Paths Summary
|
||||
43. Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2025 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Altera and sold by Altera or its authorized distributors. Please
|
||||
refer to the Altera Software License Subscription Agreements
|
||||
on the Quartus Prime software download page.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+---------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; alu ;
|
||||
; Device Family ; Cyclone V ;
|
||||
; Device Name ; 5CGXFC5C6F27C7 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Combined ;
|
||||
; Rise/Fall Delays ; Enabled ;
|
||||
+-----------------------+---------------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 2 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
----------
|
||||
; Clocks ;
|
||||
----------
|
||||
No clocks to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1100mV 85C Model Fmax Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------
|
||||
; Timing Closure Recommendations ;
|
||||
----------------------------------
|
||||
HTML report is unavailable in plain text report export.
|
||||
|
||||
|
||||
---------------------------------------
|
||||
; Slow 1100mV 85C Model Setup Summary ;
|
||||
---------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1100mV 85C Model Hold Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
------------------------------------------
|
||||
; Slow 1100mV 85C Model Recovery Summary ;
|
||||
------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1100mV 85C Model Removal Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
|
||||
-----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------
|
||||
; Slow 1100mV 85C Model Metastability Summary ;
|
||||
-----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Slow 1100mV 0C Model Fmax Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1100mV 0C Model Setup Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Slow 1100mV 0C Model Hold Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1100mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Slow 1100mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------------
|
||||
; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
|
||||
----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------
|
||||
; Slow 1100mV 0C Model Metastability Summary ;
|
||||
----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
---------------------------------------
|
||||
; Fast 1100mV 85C Model Setup Summary ;
|
||||
---------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Fast 1100mV 85C Model Hold Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
------------------------------------------
|
||||
; Fast 1100mV 85C Model Recovery Summary ;
|
||||
------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Fast 1100mV 85C Model Removal Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
|
||||
-----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------
|
||||
; Fast 1100mV 85C Model Metastability Summary ;
|
||||
-----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Fast 1100mV 0C Model Setup Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Fast 1100mV 0C Model Hold Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Fast 1100mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Fast 1100mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------------
|
||||
; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
|
||||
----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------
|
||||
; Fast 1100mV 0C Model Metastability Summary ;
|
||||
----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; Multicorner Timing Analysis Summary ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
|
||||
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Board Trace Model Assignments ;
|
||||
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; flags[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; flags[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------+
|
||||
; Input Transition Times ;
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
; op[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; op[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; A[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; B[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
+-------+--------------+-----------------+-----------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0492 V ; 0.181 V ; 0.116 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.032 V ; 0.204 V ; 0.181 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; OUT_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; OUT_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; OUT_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
; flags[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
||||
; flags[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
|
||||
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
-------------------
|
||||
; Clock Transfers ;
|
||||
-------------------
|
||||
Nothing to report.
|
||||
|
||||
|
||||
---------------
|
||||
; Report TCCS ;
|
||||
---------------
|
||||
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||||
|
||||
|
||||
---------------
|
||||
; Report RSKM ;
|
||||
---------------
|
||||
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||||
|
||||
|
||||
+------------------------------------------------+
|
||||
; Unconstrained Paths Summary ;
|
||||
+---------------------------------+-------+------+
|
||||
; Property ; Setup ; Hold ;
|
||||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 0 ; 0 ;
|
||||
; Unconstrained Input Port Paths ; 0 ; 0 ;
|
||||
; Unconstrained Output Ports ; 0 ; 0 ;
|
||||
; Unconstrained Output Port Paths ; 0 ; 0 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+--------------------------+
|
||||
; Timing Analyzer Messages ;
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||
Info: Processing started: Wed Sep 9 14:22:59 2026
|
||||
Info: Command: quartus_sta A1_Q4 -c alu
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||
Info (21077): Low junction temperature is 0 degrees C
|
||||
Info (21077): High junction temperature is 85 degrees C
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'alu.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Info (332159): No clocks to report
|
||||
Info: Analyzing Slow 1100mV 85C Model
|
||||
Info (332140): No fmax paths to report
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info: Analyzing Slow 1100mV 0C Model
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332140): No fmax paths to report
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info: Analyzing Fast 1100mV 85C Model
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info: Analyzing Fast 1100mV 0C Model
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info (332101): Design is fully constrained for setup requirements
|
||||
Info (332101): Design is fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||
Info: Peak virtual memory: 760 megabytes
|
||||
Info: Processing ended: Wed Sep 9 14:23:04 2026
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
|
||||
|
||||
Reference in new issue
Block a user