TroubleElectrical/FPGA_Uni
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

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TroubleElectrical committed 2026-09-09 14:27:11 +10:00
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commit dc32347c9b
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Quartus/A1_Q4/db/alu.hier_info
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|alu
op[0] => op[0].IN1
op[1] => op[1].IN1
op[2] => ~NO_FANOUT~
op[3] => ~NO_FANOUT~
A[0] => A[0].IN2
A[1] => A[1].IN2
A[2] => A[2].IN2
A[3] => A[3].IN2
B[0] => B[0].IN2
B[1] => B[1].IN2
B[2] => B[2].IN2
B[3] => B[3].IN2
OUT_1[0] <= <GND>
OUT_1[1] <= <GND>
OUT_1[2] <= <GND>
OUT_1[3] <= <GND>
flags[0] <= <GND>
flags[1] <= <GND>
|alu|asu:adder_unit
op[0] => operand[0].IN0
op[0] => operand[1].IN0
op[0] => operand[2].IN0
op[0] => operand[3].IN0
op[0] => _.DATAB
A[0] => _.DATAD
A[1] => _.DATAD
A[2] => _.DATAD
A[3] => OUT_CIN.IN1
A[3] => _.DATAD
B[0] => operand[0].IN1
B[1] => operand[1].IN1
B[2] => operand[2].IN1
B[3] => operand[3].IN1
OUT_1[0] <= _.SUM_OUT
OUT_1[1] <= _.SUM_OUT
OUT_1[2] <= _.SUM_OUT
OUT_1[3] <= _.SUM_OUT
COUT[0] <= _.SUM_OUT
OUT_CIN[0] <= OUT_CIN.DB_MAX_OUTPUT_PORT_TYPE
|alu|lu:logic_unit
op[0] => Mux0.IN5
op[0] => Mux1.IN5
op[0] => Mux2.IN5
op[0] => Mux3.IN5
op[1] => Mux0.IN4
op[1] => Mux1.IN4
op[1] => Mux2.IN4
op[1] => Mux3.IN4
A[0] => Y.IN0
A[0] => Y.IN0
A[0] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[1] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[2] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
A[3] => Y.IN0
B[0] => Y.IN1
B[0] => Y.IN1
B[0] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[1] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[2] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
B[3] => Y.IN1
Y[0] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE