TroubleElectrical/FPGA_Uni
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

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TroubleElectrical committed 2026-09-09 14:27:11 +10:00
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commit dc32347c9b
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Quartus/A1_Q3/output_files/asu.fit.summary
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Fitter Status : Successful - Wed Sep 9 14:14:39 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : asu
Top-level Entity Name : asu
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 4 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 15 / 364 ( 4 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )
Total DSP Blocks : 0 / 150 ( 0 % )
Total HSSI RX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )
Total HSSI TX PCSs : 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )