Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

ModelSim/work/_info

@@ -11,7 +11,7 @@ cModel Technology
 d/home/oliver/intelFPGA/20.1/modelsim_ase/bin
 vlu
 Z0 DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
-Z1 !s110 1788849038
+Z1 !s110 1788926178
 !i10b 1
 !s100 nmDP9zlMCJDa@W3_FY5m[2
 Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
@@ -22,13 +22,13 @@ Z4 d/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim
 w1788845636
 8lu.sv
 Flu.sv
-!i122 6
+!i122 8
 L0 1 16
 Z5 OV;L;2020.1;71
 r1
 !s85 0
 31
-Z6 !s108 1788849037.000000
+Z6 !s108 1788926178.000000
 !s107 lu.sv|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
 Z7 !s90 -reportprogress|300|-work|work|-sv|-stats=none|/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv|
 !i113 1
@@ -38,17 +38,17 @@ vlu_tb
 R0
 R1
 !i10b 1
-!s100 gdCQZUG[6;:5f<I_jIOd?1
+!s100 AE_liX6DCD[3>b;K6Wgf72
 R2
-IOAk[D29KmDQ0<F@G9G][k3
+IC?h=m;SY77_D:GA0FR<P^2
 R3
 S1
 R4
-w1788848626
+w1788926090
 8/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
 F/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
-!i122 6
-L0 3 57
+!i122 8
+L0 3 58
 R5
 r1
 !s85 0