TroubleElectrical/FPGA_Uni
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Updated ALU code with updated 2**width approach and assigned temporary pins to ASU (Q3)

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TroubleElectrical committed 2026-09-09 14:27:11 +10:00
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commit dc32347c9b
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ModelSim/Assignment_1_Q2.cr.mti
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/home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
Top level modules:
lu
} {} {}} /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv {1 {vlog -work work -sv -stats=none /home/oliver/Documents/FPGA_Dev/FPGA_Uni/ModelSim/lu_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module lu
-- Compiling module lu_tb
Top level modules:
lu_tb
} {} {}}