Halfway added imm,branch and mem ops

modules/register_file.sv

@@ -5,7 +5,8 @@ module register_file #(parameter width=5, parameter nregs=5)(
     input logic [0:0] clk, input logic[0:0] we,
     input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
     input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
-    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2
+    input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2,
+    input logic [nregs-1:0] RA3, output logic [2**width-1:0] RD3
 );
     localparam BW = 2**width;
     logic [2**width-1:0] regs[2**nregs];
@@ -22,5 +23,6 @@ module register_file #(parameter width=5, parameter nregs=5)(
 
     assign RD1 = regs[RA1];
     assign RD2 = regs[RA2];
+    assign RD3 = regs[RA3];
 endmodule
 `endif