Halfway added imm,branch and mem ops

modules/alu.sv

@@ -21,7 +21,6 @@ module alu #(parameter width=2)(input logic [3:0] op,
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
     always_comb begin
-        asu_flags[2] = (A == B);
         case (op) 
             4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
             4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
@@ -35,6 +34,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
             4'b1011: begin OUT_1 = ~asu_flags[0] & {{(width-1){1'b0}}, 1'b1}; flags = asu_flags; end
             default: begin OUT_1 = {(2**width){1'b0}}; flags = asu_flags; end
         endcase
+        asu_flags[2] = OUT_1 == 0;
     end
 endmodule
 `endif