Updated code such that it will compile

modules/assignment2.sv

@@ -66,9 +66,9 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		(RDST) ? instruction[15:11] : instruction[20:16], rs,
-		instruction[25:21], rt, 
 		instruction[20:16], rd,
+		(RDST) ? instruction[15:11] : instruction[20:16], rt,
+		instruction[25:21], rs, 
 		regs_out
    );
     // Always use sign-extension

modules/control_unit.sv

@@ -23,5 +23,5 @@ module control_unit (
        // TODO 
     end
 
-endmodule;
+endmodule
 `endif

modules/sign_extender.sv

@@ -8,9 +8,9 @@ module sign_extender #(in_width=4, out_width=5)(
 );
     always_comb begin
         if (op) begin
-            assign ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
+            ext_val = { {(2**(out_width-in_width)){val[2**in_width-1]}}, val};
         end else begin
-            assign ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
+            ext_val = ({{(2**(out_width-in_width)){1'b0}}, val});
         end
     end
 endmodule