Updated code such that it will compile

modules/assignment2.sv

@@ -66,9 +66,9 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	register_file #(width, 5) REGS (
 		clk, rd_we, 
-		(RDST) ? instruction[15:11] : instruction[20:16], rs,
-		instruction[25:21], rt, 
 		instruction[20:16], rd,
+		(RDST) ? instruction[15:11] : instruction[20:16], rt,
+		instruction[25:21], rs, 
 		regs_out
    );
     // Always use sign-extension