Fixed ordering for instruction counter and added module output gating for writing

modules/assignment2.sv

@@ -48,7 +48,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
     logic [2**width-1:0] rd;
     logic [0:0] rd_we;
 
-    instruction_counter PC #(romsz)(clk, pc_we, pc_addr, pc_addr_write);
+    instruction_counter PC #(width)(clk, pc_we, pc_addr_write, pc_addr);
     rom ROM #(romsz, 2**width)(pc_addr, instruction);
     instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
     instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
@@ -65,6 +65,6 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
     logic [2**width-1:0] rd_shifter;
     shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
     
+    rd = en_alu ? rd_alu : (en_shifter ? : rd_shifter : ({(2**width){1'b0}}));
 endmodule
-
 `endif