From b9623569cf2cb22c0f815ae21a8e83f814619d2f Mon Sep 17 00:00:00 2001
From: Riley King-Saunders <riley.kingsaunders@gmail.com>
Date: Tue, 13 Oct 2026 12:26:26 +1100
Subject: [PATCH] Partially implemented R-type instructions (still need to
 write rd values)

---
 modules/assignment2.sv                   | 44 +++++++++++++++++++++---
 modules/instruction_module_classifier.sv | 18 ++++++++++
 2 files changed, 57 insertions(+), 5 deletions(-)
 create mode 100644 modules/instruction_module_classifier.sv

diff --git a/modules/assignment2.sv b/modules/assignment2.sv
index ed1d9f7..92c263e 100644
--- a/modules/assignment2.sv
+++ b/modules/assignment2.sv
@@ -1,19 +1,53 @@
 `include "rom.sv"
 `include "ram.sv"
+`include "register_file.sv"
 `include "instruction_counter.sv"
 `include "instruction_classifier.sv"
+`include "instruction_module_classifier.sv"
 `include "alu.sv"
+`include "shifter.sv"
 
 
 module assignment2 #(width=5, ramsz=9, romsz=10) (input logic [0:0] clk);
-    
     logic [romsz-1:0] pc_addr;
+    logic [romsz-1:0] pc_addr_write;
     logic [0:0] pc_we;
     logic [2**width-1:0] instruction;
 
-    instruction_counter pc #(romsz)(clk, pc_we, pc_addr, pc_addr);
-    ROM rom #(romsz, 2**width)();
-    RAM ram #(ramsz,  2**width)();
-    alu alu #(width)();
+    logic[0:0] R;
+    logic[0:0] B1;
+    logic[0:0] J;
+    logic[0:0] B2;
+    logic[0:0] I;
+    logic[0:0] F;
+    logic[0:0] M;
 
+    logic [0:0] en_shifter;
+    logic [0:0] en_jmp;
+    logic [0:0] en_mul;
+    logic [0:0] en_alu;
+
+    logic [1:0] flags;
+    logic [2**width-1:0] rs;
+    logic [2**width-1:0] rt;
+    logic [2**width-1:0] rd;
+    logic [0:0] rd_we;
+
+    instruction_counter PC #(romsz)(clk, pc_we, pc_addr, pc_addr_write);
+    rom ROM #(romsz, 2**width)(pc_addr, instruction);
+    instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
+    instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], en_shifter, en_jmp, en_mul, en_alu);
+    
+    register_file REGS #(width, 32)(clk,
+        rd_we, instruction[15:11],
+        rs, instruction[25:21],
+        rt, instruction[20:16]
+    );
+
+    logic [2**width-1:0] rd_alu;
+    alu ALU #(width)(instruction[3:0], rs, rt, rd_alu, flags[1:0]);
+
+    logic [2**width-1:0] rd_shifter;
+    shifter SHIFTER #(width)(instruction[2:0], rt, rs[4:0], instruction[10:6], rd_shifter);
+    
 endmodule
\ No newline at end of file
diff --git a/modules/instruction_module_classifier.sv b/modules/instruction_module_classifier.sv
new file mode 100644
index 0000000..a880c87
--- /dev/null
+++ b/modules/instruction_module_classifier.sv
@@ -0,0 +1,18 @@
+`ifndef INSTRUCTION_CLASSIFIER_H_SV
+`define INSTRUCTION_CLASSIFIER_H_SV
+
+module instruction_module_classifier(
+    input logic [2:0] op,
+    output logic en_shifter,
+    output logic en_jmp,
+    output logic en_mul,
+    output logic en_alu,
+);
+    always_comb begin
+        en_shifter = (op & 3'b111) == 3'b000;
+        en_jmp = (op & 3'b111) == 3'b001;
+        en_mul = (op & 3'b110) == 3'b010;
+        en_alu = (op & 3'b100) == 3'b100;
+    end
+endmodule
+`endif
\ No newline at end of file