Added some delay to better test final branch/halt.

tests/mips.sv

@@ -39,6 +39,7 @@ module mips_tb();
 		$dumpvars(5, CPU.instruction);
 		$dumpvars(5, CPU.ALU);
 		$dumpvars(6, CPU.flags);
+        $dumpvars(7, CPU.rt_imm);
 
         // Zero out lower registers
         $display("Beginning MIPS tests");
@@ -96,6 +97,10 @@ module mips_tb();
 
         // Final state check
         #2;
+        #2;
+        #2;
+        #2;
+        #2;
         `TEST_CHECK(CPU.REGS.regs[8]  == 32'd10);
         `TEST_CHECK(CPU.REGS.regs[9]  == 32'd7);
         `TEST_CHECK(CPU.REGS.regs[10] == 32'd7);