TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Updated register_file.sv with proper naming scheme and 32bit width

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-10-08 15:10:40 +11:00
1 parent 102d5b4b7a
commit b49e294b7d
4 files changed
+14 -17
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A1_Q6/db/instruction_classifier.tmw_info
+4 -7
View File
@@ -1,7 +1,4 @@
start_full_compilation:s:00:00:58
start_analysis_synthesis:s:00:00:13-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:29-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation
start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation