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Updated Assignment2 with better register file module insantiation

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TroubleElectrical committed 2026-10-15 15:07:41 +11:00
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Quartus/A2/output_files/assignment2.map.rpt
+41 -11
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@@ -1,5 +1,5 @@
Analysis & Synthesis report for assignment2
Thu Oct 15 14:44:25 2026
Thu Oct 15 15:04:20 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -37,7 +37,7 @@ on the Quartus Prime software download page.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Failed - Thu Oct 15 14:44:25 2026 ;
; Analysis & Synthesis Status ; Failed - Thu Oct 15 15:04:20 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; assignment2 ;
; Top-level Entity Name ; assignment2 ;
@@ -162,16 +162,46 @@ on the Quartus Prime software download page.
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Thu Oct 15 14:44:15 2026
Info: Processing started: Thu Oct 15 15:04:10 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off assignment2 -c assignment2
Info (20032): Parallel compilation is enabled and will use up to 2 processors
Error (10267): Verilog HDL Module Instantiation error at assignment2.sv(80): cannot connect instance ports both by order and by name File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 80
Error (10112): Ignored design unit "assignment2" at assignment2.sv(16) due to previous errors File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16
Info (12021): Found 0 design units, including 0 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 400 megabytes
Error: Processing ended: Thu Oct 15 14:44:25 2026
Error: Elapsed time: 00:00:10
Error: Total CPU time (on all processors): 00:00:23
Info (12021): Found 14 design units, including 14 entities, in source file /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv
Info (12023): Found entity 1: rom File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 4
Info (12023): Found entity 2: ram File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 4
Info (12023): Found entity 3: register_file File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 4
Info (12023): Found entity 4: instruction_counter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_counter.sv Line: 4
Info (12023): Found entity 5: instruction_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_classifier.sv Line: 3
Info (12023): Found entity 6: instruction_module_classifier File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/instruction_module_classifier.sv Line: 4
Info (12023): Found entity 7: asu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/asu.sv Line: 4
Info (12023): Found entity 8: lu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/lu.sv Line: 3
Info (12023): Found entity 9: alu File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/alu.sv Line: 9
Info (12023): Found entity 10: shifter File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/shifter.sv Line: 3
Info (12023): Found entity 11: sign_extender File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 4
Info (12023): Found entity 12: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg.sv Line: 3
Info (12023): Found entity 13: seven_seg_4digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/seven_seg_4digit.sv Line: 5
Info (12023): Found entity 14: assignment2 File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 16
Info (12127): Elaborating entity "assignment2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at assignment2.sv(100): truncated value with size 32 to match size of target (10) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 100
Warning (10030): Net "flags[2]" at assignment2.sv(55) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 55
Info (12128): Elaborating entity "instruction_counter" for hierarchy "instruction_counter:PC" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 62
Info (12128): Elaborating entity "rom" for hierarchy "rom:ROM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 64
Warning (10850): Verilog HDL warning at rom.sv(16): number of words (18) in memory file does not match the number of elements in the address range [0:1023] File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 16
Warning (10030): Net "mem.data_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Warning (10030): Net "mem.waddr_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Warning (10030): Net "mem.we_a" at rom.sv(9) has no driver or initial value, using a default initial value '0' File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/rom.sv Line: 9
Info (12128): Elaborating entity "ram" for hierarchy "ram:RAM" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 67
Warning (10230): Verilog HDL assignment warning at ram.sv(23): truncated value with size 32 to match size of target (8) File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/ram.sv Line: 23
Info (12128): Elaborating entity "instruction_classifier" for hierarchy "instruction_classifier:INSTRUCTION_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 69
Info (12128): Elaborating entity "instruction_module_classifier" for hierarchy "instruction_module_classifier:INSTRUCTION_MODULE_CLASSIFIER" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 76
Info (12128): Elaborating entity "register_file" for hierarchy "register_file:REGS" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 85
Warning (10855): Verilog HDL warning at register_file.sv(14): initial value for variable regs should be constant File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/register_file.sv Line: 14
Info (12128): Elaborating entity "sign_extender" for hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88
Error (10043): Verilog HDL unsupported feature error at sign_extender.sv(11): Procedural Continuous Assignment to register is not supported File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/sign_extender.sv Line: 11
Error (12152): Can't elaborate user hierarchy "sign_extender:SIGNEXT" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/modules/assignment2.sv Line: 88
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings
Error: Peak virtual memory: 412 megabytes
Error: Processing ended: Thu Oct 15 15:04:21 2026
Error: Elapsed time: 00:00:11
Error: Total CPU time (on all processors): 00:00:24