TroubleElectrical/FPGA_Uni
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Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

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TroubleElectrical committed 2026-09-15 21:08:40 +10:00
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commit afa8d9d4db
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Quartus/A1_Q1/output_files/seven_seg.map.summary
+3 -3
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@@ -1,11 +1,11 @@
Analysis & Synthesis Status : Successful - Tue Sep 15 16:09:45 2026
Analysis & Synthesis Status : Successful - Tue Sep 15 21:06:33 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : seven_seg
Top-level Entity Name : seven_seg
Top-level Entity Name : seven_seg_2digit
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 0
Total pins : 13
Total pins : 24
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0