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Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

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TroubleElectrical committed 2026-09-15 21:08:40 +10:00
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commit afa8d9d4db
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Quartus/A1_Q1/output_files/seven_seg.map.rpt
+84 -68
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for seven_seg
Tue Sep 15 16:09:45 2026
Tue Sep 15 21:06:33 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -14,10 +14,11 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Multiplexer Restructuring Statistics (Restructuring Performed)
10. Post-Synthesis Netlist Statistics for Top Partition
11. Elapsed Time Per Partition
12. Analysis & Synthesis Messages
9. Port Connectivity Checks: "seven_seg:right_digit"
10. Port Connectivity Checks: "seven_seg:left_digit"
11. Post-Synthesis Netlist Statistics for Top Partition
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
@@ -44,14 +45,14 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:09:45 2026 ;
; Analysis & Synthesis Status ; Successful - Tue Sep 15 21:06:33 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
; Top-level Entity Name ; seven_seg_2digit ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 0 ;
; Total pins ; 13 ;
; Total pins ; 24 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 ;
; Total DSP Blocks ; 0 ;
@@ -70,7 +71,7 @@ on the Quartus Prime software download page.
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CGXFC5C6F27C7 ; ;
; Top-level entity name ; seven_seg ; seven_seg ;
; Top-level entity name ; seven_seg_2digit ; seven_seg ;
; Family name ; Cyclone V ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
@@ -176,40 +177,42 @@ on the Quartus Prime software download page.
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+
+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------+
; Resource ; Usage ;
+---------------------------------------------+--------------+
; Estimate of Logic utilization (ALMs needed) ; 4 ;
; ; ;
; Combinational ALUT usage for logic ; 8 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 7 ;
; -- 4 input functions ; 1 ;
; -- <=3 input functions ; 0 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 13 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; num[0]~input ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 60 ;
; Average fan-out ; 1.76 ;
+---------------------------------------------+--------------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+------------+
; Estimate of Logic utilization (ALMs needed) ; 8 ;
; ; ;
; Combinational ALUT usage for logic ; 15 ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 0 ;
; -- 4 input functions ; 15 ;
; -- <=3 input functions ; 0 ;
; ; ;
; Dedicated logic registers ; 0 ;
; ; ;
; I/O pins ; 24 ;
; ; ;
; Total DSP Blocks ; 0 ;
; ; ;
; Maximum fan-out node ; b[0]~input ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 99 ;
; Average fan-out ; 1.57 ;
+---------------------------------------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
; |seven_seg ; 8 (8) ; 0 (0) ; 0 ; 0 ; 13 ; 0 ; |seven_seg ; seven_seg ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
; |seven_seg_2digit ; 15 (0) ; 0 (0) ; 0 ; 0 ; 24 ; 0 ; |seven_seg_2digit ; seven_seg_2digit ; work ;
; |seven_seg:left_digit| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:left_digit ; seven_seg ; work ;
; |seven_seg:right_digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:right_digit ; seven_seg ; work ;
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -228,13 +231,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |seven_seg|Mux3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+---------------------------------------------------+
; Port Connectivity Checks: "seven_seg:right_digit" ;
+---------+-------+----------+----------------------+
; Port ; Type ; Severity ; Details ;
+---------+-------+----------+----------------------+
; rbi_inv ; Input ; Info ; Stuck at VCC ;
+---------+-------+----------+----------------------+
+--------------------------------------------------+
; Port Connectivity Checks: "seven_seg:left_digit" ;
+---------+-------+----------+---------------------+
; Port ; Type ; Severity ; Details ;
+---------+-------+----------+---------------------+
; rbi_inv ; Input ; Info ; Stuck at GND ;
+---------+-------+----------+---------------------+
+-----------------------------------------------------+
@@ -242,15 +254,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; arriav_lcell_comb ; 10 ;
; normal ; 10 ;
; 1 data inputs ; 2 ;
; 4 data inputs ; 1 ;
; 5 data inputs ; 7 ;
; boundary_port ; 13 ;
; arriav_lcell_comb ; 24 ;
; normal ; 24 ;
; 0 data inputs ; 1 ;
; 1 data inputs ; 8 ;
; 4 data inputs ; 15 ;
; boundary_port ; 24 ;
; ; ;
; Max LUT depth ; 2.00 ;
; Average LUT depth ; 1.60 ;
; Average LUT depth ; 1.72 ;
+-----------------------+-----------------------------+
@@ -269,24 +281,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Tue Sep 15 16:09:33 2026
Info: Processing started: Tue Sep 15 21:06:22 2026
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file seven_seg.sv
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 3
Info (12127): Elaborating entity "seven_seg" for the top level hierarchy
Info (12021): Found 2 design units, including 2 entities, in source file seven_seg.sv
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 4
Info (12023): Found entity 2: seven_seg_2digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 32
Info (12127): Elaborating entity "seven_seg_2digit" for the top level hierarchy
Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg:left_digit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 45
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "seg_a[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 36
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 5 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 8 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 436 megabytes
Info: Processing ended: Tue Sep 15 16:09:45 2026
Info: Elapsed time: 00:00:12
Info: Total CPU time (on all processors): 00:00:24
Info (21057): Implemented 39 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 16 output pins
Info (21061): Implemented 15 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 439 megabytes
Info: Processing ended: Tue Sep 15 21:06:33 2026
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:25