TroubleElectrical/FPGA_Uni
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Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

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TroubleElectrical committed 2026-09-15 21:08:40 +10:00
1 parent c27a04ef73
commit afa8d9d4db
79 files changed
+1935 -1153
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Quartus/A1_Q1/output_files/seven_seg.flow.rpt
+35 -32
View File
@@ -1,5 +1,5 @@
Flow report for seven_seg
Tue Sep 15 16:10:32 2026
Tue Sep 15 21:07:19 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
+-----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 15 16:10:32 2026 ;
; Flow Status ; Successful - Tue Sep 15 21:07:19 2026 ;
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
; Top-level Entity Name ; seven_seg_2digit ;
; Family ; Cyclone V ;
; Device ; 5CGXFC5C6F27C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ;
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
; Total registers ; 0 ;
; Total pins ; 13 / 364 ( 4 % ) ;
; Total pins ; 24 / 364 ( 7 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
@@ -68,32 +68,35 @@ on the Quartus Prime software download page.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/15/2026 16:09:34 ;
; Start date & time ; 09/15/2026 21:06:22 ;
; Main task ; Compilation ;
; Revision Name ; seven_seg ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.178945257408043 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 268883478169649.178947038213924 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; seven_seg_2digit ; seven_seg ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
@@ -101,12 +104,12 @@ on the Quartus Prime software download page.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:40 ;
; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:05 ; 1.0 ; 788 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ;
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 422 MB ; 00:00:24 ;
; Fitter ; 00:00:29 ; 1.0 ; 1392 MB ; 00:00:41 ;
; Assembler ; 00:00:05 ; 1.0 ; 514 MB ; 00:00:05 ;
; Timing Analyzer ; 00:00:06 ; 1.0 ; 769 MB ; 00:00:06 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
; Total ; 00:00:51 ; -- ; -- ; 00:01:17 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+