TroubleElectrical/FPGA_Uni
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Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

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TroubleElectrical committed 2026-09-15 21:08:40 +10:00
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commit afa8d9d4db
79 files changed
+1935 -1153
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Quartus/A1_Q1/output_files/seven_seg.fit.summary
+4 -4
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@@ -1,13 +1,13 @@
Fitter Status : Successful - Tue Sep 15 16:10:14 2026
Fitter Status : Successful - Tue Sep 15 21:07:03 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : seven_seg
Top-level Entity Name : seven_seg
Top-level Entity Name : seven_seg_2digit
Family : Cyclone V
Device : 5CGXFC5C6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 5 / 29,080 ( < 1 % )
Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % )
Total registers : 0
Total pins : 13 / 364 ( 4 % )
Total pins : 24 / 364 ( 7 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,567,040 ( 0 % )
Total RAM Blocks : 0 / 446 ( 0 % )