TroubleElectrical/FPGA_Uni
1
0 Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Enabled 2 segments for seven seg display decoder (Q1), most code just needs comments

Browse Source
This commit is contained in:
TroubleElectrical committed 2026-09-15 21:08:40 +10:00
1 parent c27a04ef73
commit afa8d9d4db
79 files changed
+1935 -1153
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

Quartus/A1_Q1/db/seven_seg.hier_info
+74 -1
View File
@@ -1,4 +1,77 @@
|seven_seg
|seven_seg_2digit
b[0] => b[0].IN1
b[1] => b[1].IN1
b[2] => b[2].IN1
b[3] => b[3].IN1
a[0] => a[0].IN1
a[1] => a[1].IN1
a[2] => a[2].IN1
a[3] => a[3].IN1
seg_b[0] <= seven_seg:left_digit.segments
seg_b[1] <= seven_seg:left_digit.segments
seg_b[2] <= seven_seg:left_digit.segments
seg_b[3] <= seven_seg:left_digit.segments
seg_b[4] <= seven_seg:left_digit.segments
seg_b[5] <= seven_seg:left_digit.segments
seg_b[6] <= seven_seg:left_digit.segments
seg_b[7] <= seven_seg:left_digit.segments
seg_a[0] <= seven_seg:right_digit.segments
seg_a[1] <= seven_seg:right_digit.segments
seg_a[2] <= seven_seg:right_digit.segments
seg_a[3] <= seven_seg:right_digit.segments
seg_a[4] <= seven_seg:right_digit.segments
seg_a[5] <= seven_seg:right_digit.segments
seg_a[6] <= seven_seg:right_digit.segments
seg_a[7] <= seven_seg:right_digit.segments
|seven_seg_2digit|seven_seg:left_digit
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19
num[0] => Mux2.IN19
num[0] => Mux3.IN19
num[0] => Mux4.IN19
num[0] => Mux5.IN19
num[1] => Decoder0.IN2
num[1] => Mux0.IN18
num[1] => Mux1.IN18
num[1] => Mux2.IN18
num[1] => Mux3.IN18
num[1] => Mux4.IN18
num[1] => Mux5.IN18
num[2] => Decoder0.IN1
num[2] => Mux0.IN17
num[2] => Mux1.IN17
num[2] => Mux2.IN17
num[2] => Mux3.IN17
num[2] => Mux4.IN17
num[2] => Mux5.IN17
num[3] => Decoder0.IN0
num[3] => Mux0.IN16
num[3] => Mux1.IN16
num[3] => Mux2.IN16
num[3] => Mux3.IN16
num[3] => Mux4.IN16
num[3] => Mux5.IN16
rbi_inv[0] => Mux0.IN15
rbi_inv[0] => Mux1.IN15
rbi_inv[0] => Mux2.IN15
rbi_inv[0] => Mux3.IN15
rbi_inv[0] => Mux4.IN15
rbi_inv[0] => Mux5.IN15
rbi_inv[0] => segments.DATAB
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|seven_seg_2digit|seven_seg:right_digit
num[0] => Decoder0.IN3
num[0] => Mux0.IN19
num[0] => Mux1.IN19