From ab561dd5107eab88e3132bbd9e1d409b13beae2f Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Thu, 8 Oct 2026 14:55:28 +1100 Subject: [PATCH] Implemented RAM. Possible issue by using async assignments in initial begin. --- modules/ram.sv | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 modules/ram.sv diff --git a/modules/ram.sv b/modules/ram.sv new file mode 100644 index 0000000..208fe02 --- /dev/null +++ b/modules/ram.sv @@ -0,0 +1,25 @@ +module RAM #(addrwidth=9, datawidth=5)( + input logic [0:0] clk, + input logic [2**addrwidth-1:0] addr, + input logic [0:0] we, + input logic [2**datawidth-1:0] data_in, + output logic [2**datawidth-1:0] data_out +); + + logic [7:0] mem[(2**(addrwidth+datawidth-3))-1:0]; + + // NOTE: Possible issue with assignments still pending by end of initial block + initial begin + for (integer ADDR = 0; ADDR < 2**(addrwidth+datawidth-3); ++ADDR) begin + mem[ADDR] <= 8'b0; + end + end + + always_ff(@posedge clk) begin + if (we) begin + mem[addr] <= data_in; + end + end + assign data_out = mem[addr]; + +endmodule; \ No newline at end of file