Reworked CPU to use control unit

modules/assignment2.sv

@@ -5,8 +5,7 @@
 `include "ram.sv"
 `include "register_file.sv"
 `include "instruction_counter.sv"
-`include "instruction_classifier.sv"
-`include "instruction_module_classifier.sv"
+`include "control_unit.sv"
 `include "alu.sv"
 `include "shifter.sv"
 `include "sign_extender.sv"
@@ -37,20 +36,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] instruction;
 	
 	// Instruction Classifier Intermediates
-	logic[0:0] R;
-	logic[0:0] B1;
-	logic[0:0] J;
-	logic[0:0] B2;
-	logic[0:0] I;
-	logic[0:0] F;
-	logic[0:0] M;
-	
-	// Instruction Module Classifier intermediates	
-	logic [0:0] en_shifter;
-	logic [0:0] en_jmp;
-	logic [0:0] en_mul;
-	logic [0:0] en_alu;
-	
+	logic [0:0] M2R;
+	logic [0:0] M2W;
+    logic [0:0] B;
+    logic [3:0] ALU_FN;
+	logic [0:0] ALU_SRC;
+    logic [0:0] RDST;
+	logic [0:0] RW;
+		
 	// Register File intermediates
 	logic [2:0] flags;
 	logic [2**width-1:0] rs;
@@ -63,19 +56,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	rom #(romsz, 2**width) ROM (pc_addr, instruction);
 
 	logic [2**width-1:0] rd_mem;
-	ram #(ramsz, 2**width) RAM (clk, rd_alu, B1, rt, rd_mem);
+	ram #(ramsz, 2**width) RAM (clk, rd_alu, M2W, rt, rd_mem);
 	
-	instruction_classifier INSTRUCTION_CLASSIFIER(instruction[31:26], R, B1, J, B2, I, F, M);
-	
-	instruction_module_classifier INSTRUCTION_MODULE_CLASSIFIER(instruction[5:3], 
-		en_shifter, 
-		en_jmp, 
-		en_mul, 
-		en_alu
+	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
+		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
 	);
-
+	
 	register_file #(width, 5) REGS (clk,
-		rd_we, (F) ? instruction[15:11] : instruction[20:16],
+		rd_we, (RDST) ? instruction[15:11] : instruction[20:16],
 		rs, instruction[25:21],
 		rt, instruction[20:16],
         regs_out 
@@ -89,12 +77,13 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 
 	logic [2**width-1:0] rd_alu;
 	logic [2**width-1:0] rt_alu;
-	alu #(width) ALU (instruction[3:0], rs, rt_alu, rd_alu, flags[1:0]);
-    assign rt_alu = (I) ? (rt_imm) : (rt);
+	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
+    assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
-	assign rd_we = M;
-	assign pc_we = B1 & flags[2];
+	assign rd_we = RW;
+	assign pc_we = B & flags[2];
 	assign pc_addr_write <= (rt_imm << 2) + pc_addr;
+	assign rd = (M2R) ? rd_alu : rd_mem;