Fixed compile error where iverilog didn't appreciate the string parameter type.

modules/assignment3.sv

@@ -12,7 +12,7 @@
 `include "gatereg.sv"
 `include "hazard_unit.sv"
 
-module assignment3 #(string progsrc, width=5, romsz=9, ramsz=10)(
+module assignment3 #(parameter progsrc = "", parameter width=5, parameter romsz=9, parameter ramsz=10)(
     input logic [0:0] clk, input logic [0:0] rst
 );	
     logic [31:0] regs_out [32];