From 8f9ec010ac1549d194bfaf737c0a33051ce23fe1 Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Wed, 4 Nov 2026 15:40:25 +1100 Subject: [PATCH] Updated gate register module to support arbitary delays to prevent littering uper-level code with gatereg->gatereg logic values. --- modules/gatereg.sv | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/modules/gatereg.sv b/modules/gatereg.sv index d9fdb24..43c8803 100644 --- a/modules/gatereg.sv +++ b/modules/gatereg.sv @@ -1,15 +1,18 @@ -module gatereg #(width)( +module gatereg #(width, ndelay=1)( input logic [0:0] clk, input logic [0:0] rst, input logic en[0:0], input logic [2**width-1:0] in, output logic [2**width-1:0] out ); - logic [2**width-1:0] hold_value; + logic [2**width-1:0] hold_value[ndelay]; - assign out = hold_value; + assign out = hold_value[ndelay-1]; always_ff @( posedge clk ) begin if (rst) begin hold_value <= {(2**width){0}}; end else if (en) begin - hold_value <= in; + hold_value[0] <= in; + for (int i = 1; i < ndelay; ++i) begin + hold_value[i] <= hold_value[i-1]; + end end end