Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

tests/mips.sv

@@ -12,7 +12,7 @@
     end
 
 module mips_tb(input logic [0:0] clk);
-    assignment2 #(5, 9, 10) CPU (clk);
+    assignment2 #(5) CPU (clk);
 
     integer num_errors = 0;
     initial begin