TroubleElectrical/FPGA_Uni
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Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

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riley committed 2026-10-16 03:55:57 +11:00
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@@ -12,7 +12,7 @@
end end
module mips_tb(input logic [0:0] clk); module mips_tb(input logic [0:0] clk);
assignment2 #(5, 9, 10) CPU (clk); assignment2 #(5) CPU (clk);
integer num_errors = 0; integer num_errors = 0;
initial begin initial begin