From 8675f5b8ee727ca6d40561ac07853fece54147e3 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Tue, 13 Oct 2026 12:03:55 +1100 Subject: [PATCH] Made Assignment 2 Quartus Project --- Quartus/A2/assignment2.qpf | 31 ++++++++++ Quartus/A2/assignment2.qsf | 57 +++++++++++++++++++ Quartus/A2/db/assignment2.db_info | 3 + .../A2/db/assignment2.quiproj.2400.rdr.flock | 0 4 files changed, 91 insertions(+) create mode 100644 Quartus/A2/assignment2.qpf create mode 100644 Quartus/A2/assignment2.qsf create mode 100644 Quartus/A2/db/assignment2.db_info create mode 100644 Quartus/A2/db/assignment2.quiproj.2400.rdr.flock diff --git a/Quartus/A2/assignment2.qpf b/Quartus/A2/assignment2.qpf new file mode 100644 index 0000000..581c063 --- /dev/null +++ b/Quartus/A2/assignment2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:03:16 October 13, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "12:03:16 October 13, 2026" + +# Revisions + +PROJECT_REVISION = "assignment2" diff --git a/Quartus/A2/assignment2.qsf b/Quartus/A2/assignment2.qsf new file mode 100644 index 0000000..90ea31b --- /dev/null +++ b/Quartus/A2/assignment2.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:03:16 October 13, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# assignment2_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY assignment2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:03:16 OCTOBER 13, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/assignment2.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A2/db/assignment2.db_info b/Quartus/A2/db/assignment2.db_info new file mode 100644 index 0000000..d4bd959 --- /dev/null +++ b/Quartus/A2/db/assignment2.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Tue Oct 13 12:03:19 2026 diff --git a/Quartus/A2/db/assignment2.quiproj.2400.rdr.flock b/Quartus/A2/db/assignment2.quiproj.2400.rdr.flock new file mode 100644 index 0000000..e69de29