Added Q3 sumbission and integrated all includes
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`ifndef ASU_H_SV
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`define ASU_H_SV
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`ifndef SEVEN_SEG_H_SV
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`define SEVEN_SEG_H_SV
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module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
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always_comb begin
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case (num)
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4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
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4'b0001: segments = ~(8'b00001101);
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4'b0010: segments = ~(8'b10110111);
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4'b0011: segments = ~(8'b10011111);
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4'b0100: segments = ~(8'b11001101);
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4'b0101: segments = ~(8'b11011011);
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4'b0110: segments = ~(8'b11111011);
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4'b0111: segments = ~(8'b00001111);
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4'b1000: segments = ~(8'b11111111);
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4'b1001: segments = ~(8'b11001111);
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4'b1010: segments = ~(8'b11101111);
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4'b1011: segments = ~(8'b11111001);
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4'b1100: segments = ~(8'b01110011);
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4'b1101: segments = ~(8'b10111101);
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4'b1110: segments = ~(8'b11110011);
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4'b1111: segments = ~(8'b11100011);
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default: segments = ~(8'bxxxxxxxx);
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endcase
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end
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endmodule
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`endif
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module asu #(parameter width = 2)(
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input logic [0:0] op,
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input logic[2**width-1:0] A, input logic[2**width-1:0] B,
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output logic[2**width-1:0] OUT_1, output logic[0:0] COUT, output logic[0:0] OUT_CIN
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// Used to switch between demo mode and testbench mode
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// TODO: Strip for assignment 2
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`ifdef SYNTHESIS
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, output logic[7:0] out_seg_1);
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`else
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);
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`endif
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logic [2**width-1:0] operand;
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always_comb begin
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// A + (sub) ? B : -B
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// Adds an extra bit to all operands to calculate the carry bit. Not optimal for hardware synthesis
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//operand = (B ^ {(2**width){op}});
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operand = op == 1'b0 ? B : ~B;
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{COUT, OUT_1} = A + operand + {{(2**width-1){1'b0}}, op};
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end
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// Need to do this outside of the always_comb block because parameter-based bitslicing/indexing isn't supported?
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// Cin for final bit in adder to later be xor'ed with COUT to determine if a signed overflow occured for the MIPS architecture
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assign OUT_CIN = A[2**width-1] ^ operand[2**width-1] ^ OUT_1[2**width-1];
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// Include seven segment visual output for hardware builds only
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// TODO: Strip this for assignment 2 outright
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`ifdef SYNTHESIS
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seven_seg dut(OUT_1, 1'b1, out_seg_1);
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`endif
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endmodule
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`endif
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// Testbench
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module asu_tb #(width=4)();
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logic [0:0] op;
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logic [width-1:0] A;
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logic [width-1:0] B;
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logic [width-1:0] C;
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logic [0:0] Cout;
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logic [0:0] Cin;
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logic [width-1:0] C_exp;
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logic [0:0] Cout_exp;
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logic [0:0] Cin_exp; // TODO
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asu #($clog2(width)) dut(op, A, B, C, Cout, Cin);
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integer error_count;
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initial begin
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error_count = 0;
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$display("Beginning ASU tests");
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// Test basic addition of 0+1 = 1
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op = 1'b0;
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A = {width{1'b0}};
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B = { {(width-1){1'b0}}, 1'b1};
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C_exp = { {(width-1){1'b0}}, 1'b1};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test underflow from 0-1 = UINTMAX
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op = 1'b1;
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C_exp = {(width){1'b1}};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test carry addition of 1+1 = 2
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op = 1'b0;
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A = { {(width-1){1'b0}}, 1'b1};
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B = { {(width-1){1'b0}}, 1'b1};
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C_exp = { {(width-2){1'b0}}, 2'b10};
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Cout_exp = 1'b0;
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Cin_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Test overflow from UINTMAX+1 = 0
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A = {(width){1'b1}}; // UINTMAX
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B = { {(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {(width){1'b0}};
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Cout_exp = 1'b1;
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Cin_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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// Tests INTMAX+1
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op = 1'b0;
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A = {1'b0, {(width-1){1'b1}}}; // INTMAX
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B = {{(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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Cin_exp = 1'b1;
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Cout_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b0;
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A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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C_exp = {width{1'b0}}; // 0
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Cin_exp = 1'b0;
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Cout_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b1;
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A = {1'b0, {(width-1){1'b1}}}; // INTMAX
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B = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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C_exp = {width{1'b1}}; // -1
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Cin_exp = 1'b1;
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Cout_exp = 1'b0;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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op = 1'b1;
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A = {1'b1, {(width-1){1'b0}}}; // -INTMAX
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B = {{(width-1){1'b0}}, 1'b1}; // 1
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C_exp = {1'b0, {(width-1){1'b1}}}; // INTMAX
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Cin_exp = 1'b0;
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Cout_exp = 1'b1;
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#1;
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if (C != C_exp || Cout != Cout_exp || Cin != Cin_exp || (Cin ^ Cout) != (Cin_exp ^ Cout_exp)) begin
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$display("\t\x1b[38;5;9mOp 0b%b(0b%b, 0b%b) produced 0b%b%b_%b but 0b%b%b_%b was expected\x1b[m", op, A, B, Cin, Cout, C, Cin_exp, Cout_exp, C_exp);
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error_count = error_count + 1;
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll ASU tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d ASU test(s) failing\x1b[m", error_count);
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end
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endmodule
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