Realized that, while the assembled is not binary, it is still loadable by verilog.

asm/src/ELEC4720-2026s2-Ass-02-Demo.bin

@@ -1,51 +0,0 @@
-//      $File: NewcastleUniversity/ELEC4720/2026s2/src/Code/Assignment/Ass-02-Demo.txt $
-//      $Date: 2026-10-07 01:48:03 +1100 (Wed, 07 Oct 2026) $
-//  $Revision: 2523 $
-//    $Author: Peter $
-//
-//     Course: ELEC4720(2026s2) Programmable Logic Design
-//     School: Engineering
-// University: The University of Newcastle
-//    Address: CALLAGHAN NSW 2308 Australia
-//
-//     Author: Dr Peter Stepien
-//      Email: peter.stepien@newcastle.edu.au
-//  Copyright: 2026
-	
-// Assignment 2 Demonstration Program (all instructions)
-
-// main:
-// Initialise some registers
-01084023 // subu $t0, $t0, $t0
-25090007 // addiu $t1, $t0, 7
-
-// Memory operations
-ad090000 // sw $t1, 0x0000($t0)
-8d0a0000 // lw $t2, 0x0000($t0)
-
-// Remaining arithmetic
-012a5821 // addu $t3, $t1, $t2
-012b6022 // sub $t4, $t1, $t3
-212d0003 // addi $t5, $t1, 3
-018d7020 // add $t6, $t4, $t5 
-
-// Logical
-012d8024 // and $s0, $t1, $t5
-012d8825 // or $s1, $t1, $t5 
-012d9026 // xor $s2, $t1, $t5
-012d9827 // nor $s3, $t1, $t5
-
-// Comparison
-018ea02a // slt $s4, $t4, $t6 
-018ea82b // sltu $s5, $t4, $t6
-
-// Loop to test branch
-// loop:
-25080001 // addiu $t0, $t0, 1 
-010db02b // sltu $s6, $t0, $t5
-12d4fffd // beq $s6, $s4, loop
-
-// Endless loop at end of program (FPGA)
-// finish:
-12d6ffff // beq $s6, $s6, finish
-