From 75ef513efa37e686739eacb1593d295e6dd419fb Mon Sep 17 00:00:00 2001 From: Riley King-Saunders Date: Tue, 13 Oct 2026 21:34:25 +1100 Subject: [PATCH] Added zero flag to ALU and updated testbench to not fail because of it. TODO: Add cases to test the zero flag --- modules/alu.sv | 5 +++-- tests/alu_tb.sv | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/modules/alu.sv b/modules/alu.sv index f2df22c..87f8633 100644 --- a/modules/alu.sv +++ b/modules/alu.sv @@ -8,12 +8,12 @@ // flags[1:1] = Overflow module alu #(parameter width=2)(input logic [3:0] op, input logic [2**width-1:0] A, input logic [2**width-1:0] B, - output logic [2**width-1:0] OUT_1, output logic[1:0] flags + output logic [2**width-1:0] OUT_1, output logic[2:0] flags ); // intermediate logic for handling asu output logic [0:0] asu_op; logic [2**width-1:0] asu_out; - logic [1:0] asu_flags; + logic [2:0] asu_flags; asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]); @@ -21,6 +21,7 @@ module alu #(parameter width=2)(input logic [3:0] op, lu #(width) logic_unit(op[1:0], A, B, lu_out); always_comb begin + asu_flags[2] = (A == B); case (op) 4'b0000: begin OUT_1 = asu_out; flags = asu_flags; end 4'b0001: begin OUT_1 = asu_out; flags = asu_flags; end diff --git a/tests/alu_tb.sv b/tests/alu_tb.sv index 4c4ef15..5ae3c96 100644 --- a/tests/alu_tb.sv +++ b/tests/alu_tb.sv @@ -16,14 +16,14 @@ module alu_tb #(width=2)(); logic [2**width-1:0] A_in; logic [2**width-1:0] B_in; logic [2**width-1:0] Y_out; - logic [1:0] flags_out; + logic [2:0] flags_out; localparam int NUM_TESTS = 28; logic [3:0] ops[NUM_TESTS]; logic [2**width-1:0] A_cases[NUM_TESTS]; logic [2**width-1:0] B_cases[NUM_TESTS]; logic [2**width-1:0] Y_exp[NUM_TESTS]; - logic [1:0] flags_exp[NUM_TESTS]; + logic [2:0] flags_exp[NUM_TESTS]; alu #(width) dut (op_in, A_in, B_in, Y_out, flags_out);