From 6bb6368f6c5ec880b20c15866554df9d90c155de Mon Sep 17 00:00:00 2001
From: TroubleElectrical <c3428958@uon.edu.au>
Date: Thu, 15 Oct 2026 14:23:38 +1100
Subject: [PATCH] Added external register inspection code

---
 modules/register_file.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/modules/register_file.sv b/modules/register_file.sv
index 43da9cb..8b386f2 100644
--- a/modules/register_file.sv
+++ b/modules/register_file.sv
@@ -6,6 +6,7 @@ module register_file #(parameter width=5, parameter nregs=5)(
     input logic [nregs-1:0] WA, input logic [2**width-1:0] WD,
     input logic [nregs-1:0] RA1, output logic [2**width-1:0] RD1,
     input logic [nregs-1:0] RA2, output logic [2**width-1:0] RD2
+    output logic [2**width-1:0] regs_out [2**nregs]
 );
     localparam BW = 2**width;
     logic [2**width-1:0] regs[2**nregs];
@@ -22,5 +23,6 @@ module register_file #(parameter width=5, parameter nregs=5)(
 
     assign RD1 = regs[RA1];
     assign RD2 = regs[RA2];
+    assign regs_out = regs;  // Expose registers externally
 endmodule
 `endif