Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni
Merged incomming changes
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418238472 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470144496 ""}
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||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:50:38 2026 " "Processing started: Thu Sep 3 16:50:38 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238472 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470144497 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:02:24 2026 " "Processing started: Tue Sep 15 21:02:24 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470144497 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470144497 ""}
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||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238473 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470144497 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418238798 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789470144805 ""}
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||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418238799 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789470144805 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418248175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418248175 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 2 2 " "Found 2 design units, including 2 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470154069 ""} { "Info" "ISGN_ENTITY_NAME" "2 seven_seg_2digit " "Found entity 2: seven_seg_2digit" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470154069 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470154069 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418248310 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg_2digit " "Elaborating entity \"seven_seg_2digit\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789470154206 ""}
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||||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418248991 ""}
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:left_digit " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:left_digit\"" { } { { "seven_seg.sv" "left_digit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470154211 ""}
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||||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418249329 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418249329 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789470154952 ""}
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||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418249357 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418249357 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789470155309 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470155309 ""}
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||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:50:49 2026 " "Processing ended: Thu Sep 3 16:50:49 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418249362 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "40 " "Implemented 40 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789470155342 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789470155342 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789470155342 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789470155342 ""}
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||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788418250890 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:02:35 2026 " "Processing ended: Tue Sep 15 21:02:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470155348 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470155348 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:50:50 2026 " "Processing started: Thu Sep 3 16:50:50 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1789470156795 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470156795 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:02:36 2026 " "Processing started: Tue Sep 15 21:02:36 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470156795 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1789470156795 ""}
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||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788418250948 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1789470156796 ""}
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||||||
{ "Info" "0" "" "Project = q1" { } { } 0 0 "Project = q1" 0 0 "Fitter" 0 0 1788418250949 ""}
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1789470156846 ""}
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||||||
{ "Info" "0" "" "Revision = seven_seg" { } { } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1788418250949 ""}
|
{ "Info" "0" "" "Project = q1" { } { } 0 0 "Project = q1" 0 0 "Fitter" 0 0 1789470156847 ""}
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||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418251145 ""}
|
{ "Info" "0" "" "Revision = seven_seg" { } { } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1789470156847 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418251145 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789470157029 ""}
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||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418251150 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789470157030 ""}
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||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789470157034 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470157108 ""}
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||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418251659 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470157108 ""}
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||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418251690 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789470157526 ""}
|
||||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418251743 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789470157553 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418258575 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789470157615 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258594 ""}
|
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 24 " "No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789470157886 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418258596 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789470164478 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258596 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470164536 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258597 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789470164538 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418258597 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470164539 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418258597 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470164539 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418258597 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789470164539 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418258597 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789470164539 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418258598 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418258598 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789470164540 ""}
|
||||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258614 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789470164540 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418264548 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789470164540 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789470164540 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418264548 ""}
|
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rbi\[0\] " "Node \"rbi\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "rbi\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1789470164562 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1789470164562 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418264549 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470164562 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418264549 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789470170427 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418264550 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789470170428 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418264550 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789470170428 ""}
|
||||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418264550 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789470170429 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418264553 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789470170429 ""}
|
||||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418264639 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789470170430 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265244 ""}
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789470170430 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418265528 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789470170433 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418265879 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789470170513 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265879 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470171201 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418266738 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789470171924 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418272208 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418272208 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789470172228 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418272439 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470172228 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418272442 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789470173218 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418273557 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789470178619 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789470178619 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273604 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789470178843 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789470178843 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789470178843 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418273960 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470178845 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273961 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789470179958 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418274597 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470179994 ""}
|
||||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418277269 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470180391 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:18 2026 " "Processing ended: Thu Sep 3 16:51:18 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418278082 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470180391 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788418279693 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470181168 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:19 2026 " "Processing started: Thu Sep 3 16:51:19 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""}
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470183999 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""}
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789470184273 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418280347 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1391 " "Peak virtual memory: 1391 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:04 2026 " "Processing ended: Tue Sep 15 21:03:04 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470184834 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789470184834 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418284575 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1789470186459 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:24 2026 " "Processing ended: Thu Sep 3 16:51:24 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418284739 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470186459 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:06 2026 " "Processing started: Tue Sep 15 21:03:06 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470186459 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789470186459 ""}
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788418285414 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789470186459 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788418286132 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789470187123 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:25 2026 " "Processing started: Thu Sep 3 16:51:25 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286132 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789470191389 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286133 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "503 " "Peak virtual memory: 503 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:11 2026 " "Processing ended: Tue Sep 15 21:03:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470191571 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789470191571 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418286190 ""}
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1789470192322 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418286659 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1789470193090 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418286659 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470193091 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:12 2026 " "Processing started: Tue Sep 15 21:03:12 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470193091 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470193091 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286734 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470193091 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286735 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789470193144 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418287305 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789470193614 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418287305 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789470193614 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470193681 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470193681 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789470194265 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470194265 ""}
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418287307 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418287311 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418287312 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470194266 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287313 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470194267 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287316 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789470194267 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287317 ""}
|
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789470194271 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287318 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470194272 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194273 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194277 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418287321 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194278 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418287359 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194279 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418288432 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194280 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470194281 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470194284 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470194329 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470195669 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288532 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470195772 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288535 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470195773 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195774 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195775 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418288538 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195776 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418288787 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195777 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418289393 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195778 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289431 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470195779 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470195781 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470196052 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470196791 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289433 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289434 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289435 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470196831 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470196832 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196833 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418289438 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196833 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289582 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196834 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196835 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196836 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470196837 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289585 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470196990 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289586 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289587 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289588 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470196991 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289589 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196992 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196993 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196994 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:31 2026 " "Processing ended: Thu Sep 3 16:51:31 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418291025 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196995 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788418292644 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470196996 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:32 2026 " "Processing started: Thu Sep 3 16:51:32 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470198469 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470198470 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418293402 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "789 " "Peak virtual memory: 789 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:18 2026 " "Processing ended: Tue Sep 15 21:03:18 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470198502 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789470198502 ""}
|
||||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418293464 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1789470200067 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:33 2026 " "Processing ended: Thu Sep 3 16:51:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418293508 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470200067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:03:19 2026 " "Processing started: Tue Sep 15 21:03:19 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470200067 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200067 ""}
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418294224 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200068 ""}
|
||||||
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789470200811 ""}
|
||||||
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789470200874 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:03:20 2026 " "Processing ended: Tue Sep 15 21:03:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470200924 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470200924 ""}
|
||||||
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus Prime Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470201633 ""}
|
||||||
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@@ -1,6 +1,6 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452617233 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470425268 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452617233 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:17 2026 " "Processing started: Tue Sep 15 16:10:17 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452617233 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789452617233 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470425269 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:05 2026 " "Processing started: Tue Sep 15 21:07:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470425269 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1789470425269 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789452617233 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1789470425269 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789452617910 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1789470425929 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789452622452 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1789470430344 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:22 2026 " "Processing ended: Tue Sep 15 16:10:22 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452622665 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789452622665 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "514 " "Peak virtual memory: 514 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:10 2026 " "Processing ended: Tue Sep 15 21:07:10 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470430525 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1789470430525 ""}
|
||||||
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@@ -29,23 +29,34 @@ IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The
|
|||||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||||
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||||
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
|
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
|
||||||
IO_RULES_MATRIX,Total Pass,0;13;13;0;0;13;13;0;0;0;0;0;0;8;0;0;0;0;8;0;0;0;0;8;0;13;13;0,
|
IO_RULES_MATRIX,Total Pass,0;22;22;0;0;24;22;0;0;0;0;0;0;16;0;0;0;0;16;0;0;0;0;16;0;24;24;0,
|
||||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||||
IO_RULES_MATRIX,Total Inapplicable,13;0;0;13;13;0;0;13;13;13;13;13;13;5;13;13;13;13;5;13;13;13;13;5;13;0;0;13,
|
IO_RULES_MATRIX,Total Inapplicable,24;2;2;24;24;0;2;24;24;24;24;24;24;8;24;24;24;24;8;24;24;24;24;8;24;0;0;24,
|
||||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||||
IO_RULES_MATRIX,segments[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,segments[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_b[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,num[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_a[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,rbi_inv[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_a[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,num[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_a[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,num[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_a[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_MATRIX,num[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
IO_RULES_MATRIX,seg_a[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,seg_a[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,seg_a[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,seg_a[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,b[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,b[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,b[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,b[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
|
IO_RULES_MATRIX,a[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
|
||||||
IO_RULES_SUMMARY,Total I/O Rules,28,
|
IO_RULES_SUMMARY,Total I/O Rules,28,
|
||||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
|
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
|
||||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||||
|
|||||||
Binary file not shown.
Binary file not shown.
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@@ -1,3 +1,3 @@
|
|||||||
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Version_Index = 604268800
|
Version_Index = 604268800
|
||||||
Creation_Time = Tue Sep 15 16:32:16 2026
|
Creation_Time = Tue Sep 15 20:07:32 2026
|
||||||
@@ -1,6 +1,6 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452631501 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470439149 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452631502 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:31 2026 " "Processing started: Tue Sep 15 16:10:31 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452631502 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452631502 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470439150 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:18 2026 " "Processing started: Tue Sep 15 21:07:18 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470439150 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470439150 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452631502 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470439150 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789452632297 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1789470439916 ""}
|
||||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789452632380 ""}
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1789470439976 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:32 2026 " "Processing ended: Tue Sep 15 16:10:32 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452632427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789452632427 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "670 " "Peak virtual memory: 670 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:20 2026 " "Processing ended: Tue Sep 15 21:07:20 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470440029 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1789470440029 ""}
|
||||||
@@ -1,43 +1,46 @@
|
|||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789452587402 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1789470394884 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789452587402 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1789470394885 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789452587408 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1789470394891 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452587480 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470394960 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789452587480 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1789470394960 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789452587910 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1789470395386 ""}
|
||||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789452587965 ""}
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1789470395414 ""}
|
||||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789452588119 ""}
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1789470395463 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789452595068 ""}
|
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 24 " "No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1789470395729 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452595089 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1789470402308 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789452595108 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470402364 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452595108 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1789470402367 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470402367 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1789470402367 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1789470402367 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1789470402368 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1789470402368 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789452595109 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789452595109 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1789470402368 ""}
|
||||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452595128 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1789470402368 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1789470402368 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789452601222 ""}
|
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "rbi\[0\] " "Node \"rbi\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/oliver/altera_lite/25.1std/quartus/linux64/Assignment Editor.qase" 1 { { 0 "rbi\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1789470402400 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1789470402400 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789452601223 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470402401 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789452601223 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1789470408747 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789452601224 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1789470408747 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789452601226 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1789470408748 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789452601226 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1789470408748 ""}
|
||||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789452601226 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1789470408749 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789452601230 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1789470408749 ""}
|
||||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789452601322 ""}
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1789470408750 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452602021 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1789470408753 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789452602296 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1789470408849 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789452602604 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470409568 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452602604 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1789470410209 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789452603604 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1789470410510 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789452609205 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789452609205 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470410511 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789452609431 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789452609431 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789452609431 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1789470411531 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452609434 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1789470417297 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1789470417297 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789452610686 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1789470417541 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1789470417541 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1789470417541 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452610723 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470417543 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452611103 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1789470418730 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789452611104 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470418762 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789452611860 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470419148 ""}
|
||||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789452614550 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1789470419148 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:15 2026 " "Processing ended: Tue Sep 15 16:10:15 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452615386 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789452615386 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1789470419928 ""}
|
||||||
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1789470422810 ""}
|
||||||
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1789470423088 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1392 " "Peak virtual memory: 1392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:03 2026 " "Processing ended: Tue Sep 15 21:07:03 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470423652 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1789470423652 ""}
|
||||||
@@ -1,4 +1,77 @@
|
|||||||
|seven_seg
|
|seven_seg_2digit
|
||||||
|
b[0] => b[0].IN1
|
||||||
|
b[1] => b[1].IN1
|
||||||
|
b[2] => b[2].IN1
|
||||||
|
b[3] => b[3].IN1
|
||||||
|
a[0] => a[0].IN1
|
||||||
|
a[1] => a[1].IN1
|
||||||
|
a[2] => a[2].IN1
|
||||||
|
a[3] => a[3].IN1
|
||||||
|
seg_b[0] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[1] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[2] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[3] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[4] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[5] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[6] <= seven_seg:left_digit.segments
|
||||||
|
seg_b[7] <= seven_seg:left_digit.segments
|
||||||
|
seg_a[0] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[1] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[2] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[3] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[4] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[5] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[6] <= seven_seg:right_digit.segments
|
||||||
|
seg_a[7] <= seven_seg:right_digit.segments
|
||||||
|
|
||||||
|
|
||||||
|
|seven_seg_2digit|seven_seg:left_digit
|
||||||
|
num[0] => Decoder0.IN3
|
||||||
|
num[0] => Mux0.IN19
|
||||||
|
num[0] => Mux1.IN19
|
||||||
|
num[0] => Mux2.IN19
|
||||||
|
num[0] => Mux3.IN19
|
||||||
|
num[0] => Mux4.IN19
|
||||||
|
num[0] => Mux5.IN19
|
||||||
|
num[1] => Decoder0.IN2
|
||||||
|
num[1] => Mux0.IN18
|
||||||
|
num[1] => Mux1.IN18
|
||||||
|
num[1] => Mux2.IN18
|
||||||
|
num[1] => Mux3.IN18
|
||||||
|
num[1] => Mux4.IN18
|
||||||
|
num[1] => Mux5.IN18
|
||||||
|
num[2] => Decoder0.IN1
|
||||||
|
num[2] => Mux0.IN17
|
||||||
|
num[2] => Mux1.IN17
|
||||||
|
num[2] => Mux2.IN17
|
||||||
|
num[2] => Mux3.IN17
|
||||||
|
num[2] => Mux4.IN17
|
||||||
|
num[2] => Mux5.IN17
|
||||||
|
num[3] => Decoder0.IN0
|
||||||
|
num[3] => Mux0.IN16
|
||||||
|
num[3] => Mux1.IN16
|
||||||
|
num[3] => Mux2.IN16
|
||||||
|
num[3] => Mux3.IN16
|
||||||
|
num[3] => Mux4.IN16
|
||||||
|
num[3] => Mux5.IN16
|
||||||
|
rbi_inv[0] => Mux0.IN15
|
||||||
|
rbi_inv[0] => Mux1.IN15
|
||||||
|
rbi_inv[0] => Mux2.IN15
|
||||||
|
rbi_inv[0] => Mux3.IN15
|
||||||
|
rbi_inv[0] => Mux4.IN15
|
||||||
|
rbi_inv[0] => Mux5.IN15
|
||||||
|
rbi_inv[0] => segments.DATAB
|
||||||
|
segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
||||||
|
|
||||||
|
|seven_seg_2digit|seven_seg:right_digit
|
||||||
num[0] => Decoder0.IN3
|
num[0] => Decoder0.IN3
|
||||||
num[0] => Mux0.IN19
|
num[0] => Mux0.IN19
|
||||||
num[0] => Mux1.IN19
|
num[0] => Mux1.IN19
|
||||||
|
|||||||
Binary file not shown.
@@ -15,4 +15,36 @@
|
|||||||
<TH>Input only Bidir</TH>
|
<TH>Input only Bidir</TH>
|
||||||
<TH>Output only Bidir</TH>
|
<TH>Output only Bidir</TH>
|
||||||
</TR>
|
</TR>
|
||||||
|
<TR >
|
||||||
|
<TD >right_digit</TD>
|
||||||
|
<TD >5</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >8</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
</TR>
|
||||||
|
<TR >
|
||||||
|
<TD >left_digit</TD>
|
||||||
|
<TD >5</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >8</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >1</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
<TD >0</TD>
|
||||||
|
</TR>
|
||||||
</TABLE>
|
</TABLE>
|
||||||
Binary file not shown.
@@ -1,5 +1,8 @@
|
|||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Legal Partition Candidates ;
|
; Legal Partition Candidates ;
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
|
; right_digit ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
|
; left_digit ; 5 ; 1 ; 0 ; 1 ; 8 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
|
+-------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,11 +1,13 @@
|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452574038 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470382407 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452574039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:09:33 2026 " "Processing started: Tue Sep 15 16:09:33 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452574039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452574039 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470382407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:06:22 2026 " "Processing started: Tue Sep 15 21:06:22 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470382407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470382407 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452574039 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470382408 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789452574410 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1789470382748 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789452574410 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1789470382748 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789452583455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452583455 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 2 2 " "Found 2 design units, including 2 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470391822 ""} { "Info" "ISGN_ENTITY_NAME" "2 seven_seg_2digit " "Found entity 2: seven_seg_2digit" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1789470391822 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470391822 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789452583612 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg_2digit " "Elaborating entity \"seven_seg_2digit\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1789470391962 ""}
|
||||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789452584489 ""}
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven_seg seven_seg:left_digit " "Elaborating entity \"seven_seg\" for hierarchy \"seven_seg:left_digit\"" { } { { "seven_seg.sv" "left_digit" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470391968 ""}
|
||||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789452584916 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789452584916 ""}
|
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "seg_a\[0\] GND " "Pin \"seg_a\[0\]\" is stuck at GND" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 36 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1789470392591 "|seven_seg_2digit|seg_a[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1789470392591 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789452585041 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789452585041 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789452585041 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789452585041 ""}
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1789470392705 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:09:45 2026 " "Processing ended: Tue Sep 15 16:09:45 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452585047 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789452585047 ""}
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1789470393089 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1789470393089 ""}
|
||||||
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1789470393122 ""} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Implemented 16 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1789470393122 ""} { "Info" "ICUT_CUT_TM_LCELLS" "15 " "Implemented 15 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1789470393122 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1789470393122 ""}
|
||||||
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:06:33 2026 " "Processing ended: Tue Sep 15 21:06:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470393128 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1789470393128 ""}
|
||||||
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|
|||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789452624355 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1789470432010 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789452624356 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 16:10:24 2026 " "Processing started: Tue Sep 15 16:10:24 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789452624356 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452624356 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1789470432010 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 15 21:07:11 2026 " "Processing started: Tue Sep 15 21:07:11 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1789470432010 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470432010 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452624356 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470432011 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789452624432 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1789470432068 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789452624945 ""}
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1789470432597 ""}
|
||||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789452624945 ""}
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1789470432598 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625018 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470432666 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625018 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470432666 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789452625598 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1789470433270 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452625599 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452625599 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452625600 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470433271 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789452625600 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1789470433272 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452625600 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470433272 ""}
|
||||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789452625601 ""}
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1789470433273 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789452625605 ""}
|
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1789470433277 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452625605 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470433278 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625607 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433279 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625618 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433283 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625619 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433284 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625620 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433287 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625620 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433288 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452625621 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470433289 ""}
|
||||||
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452625623 ""}
|
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470433293 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452625661 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470433344 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452627007 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470434738 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452627088 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452627088 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452627088 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452627089 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470434835 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627089 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434836 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627091 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434837 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627092 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434838 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627093 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434839 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627094 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434840 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452627094 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470434840 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789452627096 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1789470434842 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789452627365 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1789470435111 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789452628090 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1789470435850 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452628130 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452628130 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470435895 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628132 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435897 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628133 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435898 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628133 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435899 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628134 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435899 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628135 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470435900 ""}
|
||||||
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789452628136 ""}
|
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1789470435903 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789452628295 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789452628295 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
|
||||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789452628295 ""}
|
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
|
||||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789452628296 ""}
|
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1789470436058 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628297 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436059 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628298 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436060 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628299 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436061 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628299 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436062 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789452628300 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1789470436062 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452629766 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470437535 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789452629766 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1789470437536 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 16:10:29 2026 " "Processing ended: Tue Sep 15 16:10:29 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789452629798 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789452629798 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "769 " "Peak virtual memory: 769 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 15 21:07:17 2026 " "Processing ended: Tue Sep 15 21:07:17 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1789470437560 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1789470437560 ""}
|
||||||
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@@ -1,4 +1,7 @@
|
|||||||
start_full_compilation:s
|
start_full_compilation:s:00:00:59
|
||||||
start_assembler:s-start_full_compilation
|
start_analysis_synthesis:s:00:00:12-start_full_compilation
|
||||||
start_timing_analyzer:s-start_full_compilation
|
start_analysis_elaboration:s-start_full_compilation
|
||||||
start_eda_netlist_writer:s-start_full_compilation
|
start_fitter:s:00:00:31-start_full_compilation
|
||||||
|
start_assembler:s:00:00:07-start_full_compilation
|
||||||
|
start_timing_analyzer:s:00:00:07-start_full_compilation
|
||||||
|
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|
||||||
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@@ -4,55 +4,95 @@
|
|||||||
"name" : "Top",
|
"name" : "Top",
|
||||||
"pins" : [
|
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|
||||||
{
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
"name" : "segments[3]",
|
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|
||||||
"strict" : false
|
"strict" : false
|
||||||
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|
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|
||||||
{
|
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|
||||||
"name" : "segments[4]",
|
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|
||||||
"strict" : false
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
{
|
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|
||||||
"name" : "segments[6]",
|
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|
||||||
"strict" : false
|
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|
||||||
},
|
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|
||||||
{
|
{
|
||||||
"name" : "segments[7]",
|
"name" : "seg_b[7]",
|
||||||
"strict" : false
|
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|
||||||
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|
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|
||||||
{
|
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|
||||||
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|
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|
||||||
"strict" : false
|
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|
||||||
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|
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|
||||||
{
|
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|
||||||
"name" : "rbi_inv[0]",
|
"name" : "seg_a[2]",
|
||||||
"strict" : false
|
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|
||||||
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|
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|
||||||
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|
||||||
"name" : "num[3]",
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
{
|
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|
||||||
"name" : "num[1]",
|
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|
||||||
"strict" : false
|
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|
||||||
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|
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|
||||||
{
|
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|
||||||
"name" : "num[2]",
|
"name" : "seg_a[5]",
|
||||||
|
"strict" : false
|
||||||
|
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|
||||||
|
{
|
||||||
|
"name" : "seg_a[6]",
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
"strict" : false
|
||||||
|
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|
||||||
|
{
|
||||||
|
"name" : "b[1]",
|
||||||
|
"strict" : false
|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
{
|
||||||
|
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|
||||||
|
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|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
"strict" : false
|
||||||
|
},
|
||||||
|
{
|
||||||
|
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|
||||||
|
"strict" : false
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name" : "a[2]",
|
||||||
|
"strict" : false
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name" : "a[3]",
|
||||||
"strict" : false
|
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|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
|
|||||||
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@@ -1,5 +1,5 @@
|
|||||||
Assembler report for seven_seg
|
Assembler report for seven_seg
|
||||||
Tue Sep 15 16:10:22 2026
|
Tue Sep 15 21:07:10 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -38,9 +38,9 @@ on the Quartus Prime software download page.
|
|||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Tue Sep 15 16:10:22 2026 ;
|
; Assembler Status ; Successful - Tue Sep 15 21:07:10 2026 ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
; Top-level Entity Name ; seven_seg ;
|
; Top-level Entity Name ; seven_seg_2digit ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
; Device ; 5CGXFC5C6F27C7 ;
|
; Device ; 5CGXFC5C6F27C7 ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
@@ -67,8 +67,8 @@ on the Quartus Prime software download page.
|
|||||||
+----------------+------------------------+
|
+----------------+------------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+----------------+------------------------+
|
+----------------+------------------------+
|
||||||
; JTAG usercode ; 0x00781CB4 ;
|
; JTAG usercode ; 0x007840FC ;
|
||||||
; Checksum ; 0x00781CB4 ;
|
; Checksum ; 0x007840FC ;
|
||||||
+----------------+------------------------+
|
+----------------+------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -78,13 +78,13 @@ on the Quartus Prime software download page.
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Assembler
|
Info: Running Quartus Prime Assembler
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 15 16:10:17 2026
|
Info: Processing started: Tue Sep 15 21:07:05 2026
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 521 megabytes
|
Info: Peak virtual memory: 514 megabytes
|
||||||
Info: Processing ended: Tue Sep 15 16:10:22 2026
|
Info: Processing ended: Tue Sep 15 21:07:10 2026
|
||||||
Info: Elapsed time: 00:00:05
|
Info: Elapsed time: 00:00:05
|
||||||
Info: Total CPU time (on all processors): 00:00:05
|
Info: Total CPU time (on all processors): 00:00:05
|
||||||
|
|
||||||
|
|||||||
@@ -1 +1 @@
|
|||||||
Tue Sep 15 16:10:33 2026
|
Tue Sep 15 21:07:20 2026
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
EDA Netlist Writer report for seven_seg
|
EDA Netlist Writer report for seven_seg
|
||||||
Tue Sep 15 16:10:32 2026
|
Tue Sep 15 21:07:19 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -37,9 +37,9 @@ on the Quartus Prime software download page.
|
|||||||
+-------------------------------------------------------------------+
|
+-------------------------------------------------------------------+
|
||||||
; EDA Netlist Writer Summary ;
|
; EDA Netlist Writer Summary ;
|
||||||
+---------------------------+---------------------------------------+
|
+---------------------------+---------------------------------------+
|
||||||
; EDA Netlist Writer Status ; Successful - Tue Sep 15 16:10:32 2026 ;
|
; EDA Netlist Writer Status ; Successful - Tue Sep 15 21:07:19 2026 ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
; Top-level Entity Name ; seven_seg ;
|
; Top-level Entity Name ; seven_seg_2digit ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
; Simulation Files Creation ; Successful ;
|
; Simulation Files Creation ; Successful ;
|
||||||
+---------------------------+---------------------------------------+
|
+---------------------------+---------------------------------------+
|
||||||
@@ -81,14 +81,14 @@ on the Quartus Prime software download page.
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime EDA Netlist Writer
|
Info: Running Quartus Prime EDA Netlist Writer
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 15 16:10:31 2026
|
Info: Processing started: Tue Sep 15 21:07:18 2026
|
||||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg
|
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool
|
Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool
|
||||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||||
Info: Peak virtual memory: 658 megabytes
|
Info: Peak virtual memory: 670 megabytes
|
||||||
Info: Processing ended: Tue Sep 15 16:10:32 2026
|
Info: Processing ended: Tue Sep 15 21:07:20 2026
|
||||||
Info: Elapsed time: 00:00:01
|
Info: Elapsed time: 00:00:02
|
||||||
Info: Total CPU time (on all processors): 00:00:01
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
Fitter report for seven_seg
|
Fitter report for seven_seg
|
||||||
Tue Sep 15 16:10:14 2026
|
Tue Sep 15 21:07:03 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -10,27 +10,28 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
|||||||
2. Fitter Summary
|
2. Fitter Summary
|
||||||
3. Fitter Settings
|
3. Fitter Settings
|
||||||
4. Parallel Compilation
|
4. Parallel Compilation
|
||||||
5. Incremental Compilation Preservation Summary
|
5. Ignored Assignments
|
||||||
6. Incremental Compilation Partition Settings
|
6. Incremental Compilation Preservation Summary
|
||||||
7. Incremental Compilation Placement Preservation
|
7. Incremental Compilation Partition Settings
|
||||||
8. Pin-Out File
|
8. Incremental Compilation Placement Preservation
|
||||||
9. Fitter Resource Usage Summary
|
9. Pin-Out File
|
||||||
10. Fitter Partition Statistics
|
10. Fitter Resource Usage Summary
|
||||||
11. Input Pins
|
11. Fitter Partition Statistics
|
||||||
12. Output Pins
|
12. Input Pins
|
||||||
13. I/O Bank Usage
|
13. Output Pins
|
||||||
14. All Package Pins
|
14. I/O Bank Usage
|
||||||
15. I/O Assignment Warnings
|
15. All Package Pins
|
||||||
16. Fitter Resource Utilization by Entity
|
16. I/O Assignment Warnings
|
||||||
17. Delay Chain Summary
|
17. Fitter Resource Utilization by Entity
|
||||||
18. Pad To Core Delay Chain Fanout
|
18. Delay Chain Summary
|
||||||
19. Routing Usage Summary
|
19. Pad To Core Delay Chain Fanout
|
||||||
20. I/O Rules Summary
|
20. Routing Usage Summary
|
||||||
21. I/O Rules Details
|
21. I/O Rules Summary
|
||||||
22. I/O Rules Matrix
|
22. I/O Rules Details
|
||||||
23. Fitter Device Options
|
23. I/O Rules Matrix
|
||||||
24. Operating Settings and Conditions
|
24. Fitter Device Options
|
||||||
25. Fitter Messages
|
25. Operating Settings and Conditions
|
||||||
|
26. Fitter Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -57,16 +58,16 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Fitter Summary ;
|
; Fitter Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Fitter Status ; Successful - Tue Sep 15 16:10:14 2026 ;
|
; Fitter Status ; Successful - Tue Sep 15 21:07:03 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
; Top-level Entity Name ; seven_seg ;
|
; Top-level Entity Name ; seven_seg_2digit ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
; Device ; 5CGXFC5C6F27C7 ;
|
; Device ; 5CGXFC5C6F27C7 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ;
|
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
|
||||||
; Total registers ; 0 ;
|
; Total registers ; 0 ;
|
||||||
; Total pins ; 13 / 364 ( 4 % ) ;
|
; Total pins ; 24 / 364 ( 7 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
||||||
; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
|
; Total RAM Blocks ; 0 / 446 ( 0 % ) ;
|
||||||
@@ -152,18 +153,31 @@ on the Quartus Prime software download page.
|
|||||||
; ; ;
|
; ; ;
|
||||||
; Usage by Processor ; % Time Used ;
|
; Usage by Processor ; % Time Used ;
|
||||||
; Processor 1 ; 100.0% ;
|
; Processor 1 ; 100.0% ;
|
||||||
; Processor 2 ; 0.3% ;
|
; Processor 2 ; 0.2% ;
|
||||||
+----------------------------+-------------+
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
|
+----------------------------------------------------------------------------------------------+
|
||||||
|
; Ignored Assignments ;
|
||||||
|
+--------------+------------------+--------------+------------+---------------+----------------+
|
||||||
|
; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
|
||||||
|
+--------------+------------------+--------------+------------+---------------+----------------+
|
||||||
|
; Location ; ; ; rbi[0] ; PIN_AE19 ; QSF Assignment ;
|
||||||
|
; I/O Standard ; seven_seg_2digit ; ; b ; 1.2 V ; QSF Assignment ;
|
||||||
|
; I/O Standard ; seven_seg_2digit ; ; rbi[0] ; 1.2 V ; QSF Assignment ;
|
||||||
|
; I/O Standard ; seven_seg_2digit ; ; seg_a ; 1.2 V ; QSF Assignment ;
|
||||||
|
; I/O Standard ; seven_seg_2digit ; ; seg_b ; 1.2 V ; QSF Assignment ;
|
||||||
|
+--------------+------------------+--------------+------------+---------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------+
|
||||||
; Incremental Compilation Preservation Summary ;
|
; Incremental Compilation Preservation Summary ;
|
||||||
+---------------------+-------------------+----------------------------+--------------------------+
|
+---------------------+-------------------+----------------------------+--------------------------+
|
||||||
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
||||||
+---------------------+-------------------+----------------------------+--------------------------+
|
+---------------------+-------------------+----------------------------+--------------------------+
|
||||||
; Placement (by node) ; ; ; ;
|
; Placement (by node) ; ; ; ;
|
||||||
; -- Requested ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 ) ;
|
; -- Requested ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ;
|
||||||
; -- Achieved ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 ) ; 0.00 % ( 0 / 35 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ; 0.00 % ( 0 / 64 ) ;
|
||||||
; ; ; ; ;
|
; ; ; ; ;
|
||||||
; Routing (by net) ; ; ; ;
|
; Routing (by net) ; ; ; ;
|
||||||
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
||||||
@@ -186,7 +200,7 @@ on the Quartus Prime software download page.
|
|||||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||||
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
||||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||||
; Top ; 0.00 % ( 0 / 35 ) ; N/A ; Source File ; N/A ; ;
|
; Top ; 0.00 % ( 0 / 64 ) ; N/A ; Source File ; N/A ; ;
|
||||||
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
|
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
|
||||||
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
||||||
|
|
||||||
@@ -202,14 +216,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
+-------------------------------------------------------------+--------------------+-------+
|
+-------------------------------------------------------------+--------------------+-------+
|
||||||
; Resource ; Usage ; % ;
|
; Resource ; Usage ; % ;
|
||||||
+-------------------------------------------------------------+--------------------+-------+
|
+-------------------------------------------------------------+--------------------+-------+
|
||||||
; Logic utilization (ALMs needed / total ALMs on device) ; 5 / 29,080 ; < 1 % ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29,080 ; < 1 % ;
|
||||||
; ALMs needed [=A-B+C] ; 5 ; ;
|
; ALMs needed [=A-B+C] ; 8 ; ;
|
||||||
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29,080 ; < 1 % ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29,080 ; < 1 % ;
|
||||||
; [a] ALMs used for LUT logic and registers ; 0 ; ;
|
; [a] ALMs used for LUT logic and registers ; 0 ; ;
|
||||||
; [b] ALMs used for LUT logic ; 8 ; ;
|
; [b] ALMs used for LUT logic ; 8 ; ;
|
||||||
; [c] ALMs used for registers ; 0 ; ;
|
; [c] ALMs used for registers ; 0 ; ;
|
||||||
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
||||||
; [B] Estimate of ALMs recoverable by dense packing ; 3 / 29,080 ; < 1 % ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29,080 ; 0 % ;
|
||||||
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29,080 ; 0 % ;
|
||||||
; [a] Due to location constrained logic ; 0 ; ;
|
; [a] Due to location constrained logic ; 0 ; ;
|
||||||
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
|
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
|
||||||
@@ -218,15 +232,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Difficulty packing design ; Low ; ;
|
; Difficulty packing design ; Low ; ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Total LABs: partially or completely used ; 2 / 2,908 ; < 1 % ;
|
; Total LABs: partially or completely used ; 3 / 2,908 ; < 1 % ;
|
||||||
; -- Logic LABs ; 2 ; ;
|
; -- Logic LABs ; 3 ; ;
|
||||||
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Combinational ALUT usage for logic ; 9 ; ;
|
; Combinational ALUT usage for logic ; 16 ; ;
|
||||||
; -- 7 input functions ; 0 ; ;
|
; -- 7 input functions ; 0 ; ;
|
||||||
; -- 6 input functions ; 0 ; ;
|
; -- 6 input functions ; 0 ; ;
|
||||||
; -- 5 input functions ; 7 ; ;
|
; -- 5 input functions ; 0 ; ;
|
||||||
; -- 4 input functions ; 1 ; ;
|
; -- 4 input functions ; 15 ; ;
|
||||||
; -- <=3 input functions ; 1 ; ;
|
; -- <=3 input functions ; 1 ; ;
|
||||||
; Combinational ALUT usage for route-throughs ; 0 ; ;
|
; Combinational ALUT usage for route-throughs ; 0 ; ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
@@ -239,7 +253,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; -- Routing optimization registers ; 0 ; ;
|
; -- Routing optimization registers ; 0 ; ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Virtual pins ; 0 ; ;
|
; Virtual pins ; 0 ; ;
|
||||||
; I/O pins ; 13 / 364 ; 4 % ;
|
; I/O pins ; 24 / 364 ; 7 % ;
|
||||||
; -- Clock pins ; 0 / 14 ; 0 % ;
|
; -- Clock pins ; 0 / 14 ; 0 % ;
|
||||||
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
|
; -- Dedicated input pins ; 0 / 23 ; 0 % ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
@@ -271,11 +285,11 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
||||||
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
||||||
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
|
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ;
|
||||||
; Peak interconnect usage (total/H/V) ; 0.1% / 0.2% / 0.1% ; ;
|
; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.2% ; ;
|
||||||
; Maximum fan-out ; 8 ; ;
|
; Maximum fan-out ; 8 ; ;
|
||||||
; Highest non-global fan-out ; 8 ; ;
|
; Highest non-global fan-out ; 8 ; ;
|
||||||
; Total fan-out ; 60 ; ;
|
; Total fan-out ; 99 ; ;
|
||||||
; Average fan-out ; 1.71 ; ;
|
; Average fan-out ; 1.55 ; ;
|
||||||
+-------------------------------------------------------------+--------------------+-------+
|
+-------------------------------------------------------------+--------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
@@ -284,14 +298,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||||
; Statistic ; Top ; hard_block:auto_generated_inst ;
|
; Statistic ; Top ; hard_block:auto_generated_inst ;
|
||||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||||
; Logic utilization (ALMs needed / total ALMs on device) ; 5 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||||
; ALMs needed [=A-B+C] ; 5 ; 0 ;
|
; ALMs needed [=A-B+C] ; 8 ; 0 ;
|
||||||
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 8 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
||||||
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
|
; [a] ALMs used for LUT logic and registers ; 0 ; 0 ;
|
||||||
; [b] ALMs used for LUT logic ; 8 ; 0 ;
|
; [b] ALMs used for LUT logic ; 8 ; 0 ;
|
||||||
; [c] ALMs used for registers ; 0 ; 0 ;
|
; [c] ALMs used for registers ; 0 ; 0 ;
|
||||||
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
|
||||||
; [B] Estimate of ALMs recoverable by dense packing ; 3 / 29080 ( < 1 % ) ; 0 / 29080 ( 0 % ) ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||||
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 0 / 29080 ( 0 % ) ; 0 / 29080 ( 0 % ) ;
|
||||||
; [a] Due to location constrained logic ; 0 ; 0 ;
|
; [a] Due to location constrained logic ; 0 ; 0 ;
|
||||||
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
|
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
|
||||||
@@ -300,15 +314,15 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Difficulty packing design ; Low ; Low ;
|
; Difficulty packing design ; Low ; Low ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Total LABs: partially or completely used ; 2 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
|
; Total LABs: partially or completely used ; 3 / 2908 ( < 1 % ) ; 0 / 2908 ( 0 % ) ;
|
||||||
; -- Logic LABs ; 2 ; 0 ;
|
; -- Logic LABs ; 3 ; 0 ;
|
||||||
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Combinational ALUT usage for logic ; 9 ; 0 ;
|
; Combinational ALUT usage for logic ; 16 ; 0 ;
|
||||||
; -- 7 input functions ; 0 ; 0 ;
|
; -- 7 input functions ; 0 ; 0 ;
|
||||||
; -- 6 input functions ; 0 ; 0 ;
|
; -- 6 input functions ; 0 ; 0 ;
|
||||||
; -- 5 input functions ; 7 ; 0 ;
|
; -- 5 input functions ; 0 ; 0 ;
|
||||||
; -- 4 input functions ; 1 ; 0 ;
|
; -- 4 input functions ; 15 ; 0 ;
|
||||||
; -- <=3 input functions ; 1 ; 0 ;
|
; -- <=3 input functions ; 1 ; 0 ;
|
||||||
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
|
; Combinational ALUT usage for route-throughs ; 0 ; 0 ;
|
||||||
; Memory ALUT usage ; 0 ; 0 ;
|
; Memory ALUT usage ; 0 ; 0 ;
|
||||||
@@ -325,7 +339,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; ; ; ;
|
; ; ; ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Virtual pins ; 0 ; 0 ;
|
; Virtual pins ; 0 ; 0 ;
|
||||||
; I/O pins ; 13 ; 0 ;
|
; I/O pins ; 24 ; 0 ;
|
||||||
; I/O registers ; 0 ; 0 ;
|
; I/O registers ; 0 ; 0 ;
|
||||||
; Total block memory bits ; 0 ; 0 ;
|
; Total block memory bits ; 0 ; 0 ;
|
||||||
; Total block memory implementation bits ; 0 ; 0 ;
|
; Total block memory implementation bits ; 0 ; 0 ;
|
||||||
@@ -337,7 +351,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; -- Registered Output Connections ; 0 ; 0 ;
|
; -- Registered Output Connections ; 0 ; 0 ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Internal Connections ; ; ;
|
; Internal Connections ; ; ;
|
||||||
; -- Total Connections ; 60 ; 0 ;
|
; -- Total Connections ; 99 ; 0 ;
|
||||||
; -- Registered Connections ; 0 ; 0 ;
|
; -- Registered Connections ; 0 ; 0 ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; External Connections ; ; ;
|
; External Connections ; ; ;
|
||||||
@@ -345,8 +359,8 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Partition Interface ; ; ;
|
; Partition Interface ; ; ;
|
||||||
; -- Input Ports ; 5 ; 0 ;
|
; -- Input Ports ; 8 ; 0 ;
|
||||||
; -- Output Ports ; 8 ; 0 ;
|
; -- Output Ports ; 16 ; 0 ;
|
||||||
; -- Bidir Ports ; 0 ; 0 ;
|
; -- Bidir Ports ; 0 ; 0 ;
|
||||||
; ; ; ;
|
; ; ; ;
|
||||||
; Registered Ports ; ; ;
|
; Registered Ports ; ; ;
|
||||||
@@ -365,33 +379,44 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
+-------------------------------------------------------------+---------------------+--------------------------------+
|
+-------------------------------------------------------------+---------------------+--------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Input Pins ;
|
; Input Pins ;
|
||||||
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
||||||
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||||
; num[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
|
; a[0] ; AC9 ; 3B ; 14 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
; num[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
|
; a[1] ; AE10 ; 4A ; 36 ; 0 ; 51 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
; num[2] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
|
; a[2] ; AD13 ; 4A ; 34 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
; num[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
|
; a[3] ; AC8 ; 3B ; 14 ; 0 ; 51 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
; rbi_inv[0] ; AE19 ; 4A ; 50 ; 0 ; 34 ; 7 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; User ; no ;
|
; b[0] ; W11 ; 3B ; 10 ; 0 ; 40 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
+------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
; b[1] ; AB10 ; 3B ; 12 ; 0 ; 34 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
|
; b[2] ; V10 ; 3B ; 17 ; 0 ; 74 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
|
; b[3] ; AC10 ; 3B ; 12 ; 0 ; 51 ; 8 ; 0 ; no ; no ; no ; no ; Off ; 1.2 V ; Off ; -- ; User ; no ;
|
||||||
|
+------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Output Pins ;
|
; Output Pins ;
|
||||||
+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
||||||
+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||||
; segments[0] ; F7 ; 8A ; 14 ; 61 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[0] ; G12 ; 7A ; 36 ; 61 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||||
; segments[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[1] ; V19 ; 4A ; 66 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[2] ; V18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[3] ; V17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[4] ; W18 ; 4A ; 66 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[5] ; Y20 ; 4A ; 65 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[6] ; Y19 ; 4A ; 65 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
; segments[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; seg_a[7] ; Y18 ; 4A ; 62 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
; seg_b[0] ; AD21 ; 4A ; 57 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
|
||||||
|
; seg_b[1] ; AA18 ; 4A ; 62 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[2] ; AD26 ; 4A ; 64 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[3] ; AB19 ; 4A ; 65 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[4] ; AE26 ; 4A ; 64 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[5] ; AE25 ; 4A ; 62 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[6] ; AC19 ; 4A ; 65 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
; seg_b[7] ; AF24 ; 4A ; 62 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 1.2 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
||||||
|
+----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------+
|
||||||
@@ -402,13 +427,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
; B1L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||||
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
; B0L ; 0 / 14 ( 0 % ) ; -- ; -- ; -- ;
|
||||||
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
; 3A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||||
; 3B ; 2 / 32 ( 6 % ) ; 2.5V ; -- ; 2.5V ;
|
; 3B ; 6 / 32 ( 19 % ) ; 1.2V ; -- ; 2.5V ;
|
||||||
; 4A ; 10 / 80 ( 13 % ) ; 2.5V ; -- ; 2.5V ;
|
; 4A ; 17 / 80 ( 21 % ) ; 1.2V ; -- ; 2.5V ;
|
||||||
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
; 5A ; 0 / 16 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||||
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
; 5B ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||||
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
; 6A ; 0 / 48 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||||
; 7A ; 0 / 80 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
; 7A ; 1 / 80 ( 1 % ) ; 1.2V ; -- ; 2.5V ;
|
||||||
; 8A ; 1 / 32 ( 3 % ) ; 2.5V ; -- ; 2.5V ;
|
; 8A ; 0 / 32 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
|
||||||
+----------+------------------+---------------+--------------+---------------+
|
+----------+------------------+---------------+--------------+---------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -425,7 +450,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A7 ; 348 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A8 ; 308 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A9 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A9 ; 310 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A10 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; A10 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; A11 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A11 ; 322 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A12 ; 332 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A12 ; 332 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A13 ; 330 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A13 ; 330 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -435,7 +460,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A17 ; 292 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A18 ; 290 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A19 ; 288 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A20 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; A20 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; A21 ; 274 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A21 ; 274 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A22 ; 270 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A22 ; 270 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; A23 ; 268 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; A23 ; 268 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -450,7 +475,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AA7 ; 47 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA8 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
; AA9 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||||
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA10 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA11 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||||
; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
@@ -458,9 +483,9 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AA15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AA16 ; 113 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AA18 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AA18 ; 151 ; 4A ; seg_b[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AA20 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AA21 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; AA22 ; 170 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; AA23 ; 172 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -476,16 +501,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
; AB7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
|
||||||
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AB8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AB9 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AB10 ; 61 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB10 ; 61 ; 3B ; b[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB11 ; 63 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB12 ; 65 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AB13 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AB14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB15 ; 105 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB16 ; 111 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB17 ; 129 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AB18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AB19 ; 160 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB19 ; 160 ; 4A ; seg_b[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AB20 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AB21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AB22 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -500,18 +525,18 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AC5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AC6 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
; AC7 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||||
; AC8 ; 62 ; 3B ; num[3] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; AC8 ; 62 ; 3B ; a[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AC9 ; 64 ; 3B ; num[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; AC9 ; 64 ; 3B ; a[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AC10 ; 59 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC10 ; 59 ; 3B ; b[3] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AC11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
|
; AC12 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||||
; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC13 ; 102 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC14 ; 104 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC15 ; 103 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AC16 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC17 ; 127 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC18 ; 120 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC19 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC19 ; 158 ; 4A ; seg_b[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AC20 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AC21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; AC22 ; 166 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -527,24 +552,24 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD6 ; 51 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD7 ; 53 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD8 ; 73 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AD9 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD10 ; 96 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD11 ; 88 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD12 ; 91 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD13 ; 93 ; 4A ; num[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; AD13 ; 93 ; 4A ; a[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AD14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
; AD15 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||||
; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD16 ; 119 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD17 ; 121 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD18 ; 118 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AD19 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD20 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD21 ; 139 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD21 ; 139 ; 4A ; seg_b[0] ; output ; 1.2 V ; ; Column I/O ; N ; no ; Off ;
|
||||||
; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD22 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD23 ; 144 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AD24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; AD25 ; 191 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; AD26 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AD26 ; 157 ; 4A ; seg_b[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
; AE3 ; 22 ; B0L ; GXB_NC ; ; ; ; -- ; ; -- ; -- ;
|
||||||
@@ -554,23 +579,23 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AE7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE8 ; 71 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE9 ; 77 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE10 ; 94 ; 4A ; num[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; AE10 ; 94 ; 4A ; a[1] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE11 ; 86 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AE12 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE13 ; 109 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE14 ; 112 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE15 ; 135 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE16 ; 137 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AE17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE18 ; 117 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE19 ; 125 ; 4A ; rbi_inv[0] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; AE19 ; 125 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE20 ; 133 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE21 ; 131 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AE22 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE23 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE24 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AE25 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE25 ; 152 ; 4A ; seg_b[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AE26 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AE26 ; 155 ; 4A ; seg_b[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AF4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
@@ -584,7 +609,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF12 ; 99 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF13 ; 107 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF14 ; 110 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; AF15 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF16 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF17 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF18 ; 115 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -593,7 +618,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF21 ; 128 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF22 ; 126 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF23 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; AF24 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; AF24 ; 150 ; 4A ; seg_b[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; AF25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;
|
; B1 ; ; ; RREF ; ; ; ; -- ; ; -- ; -- ;
|
||||||
; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
@@ -607,7 +632,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; B10 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B10 ; 320 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B11 ; 334 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B11 ; 334 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B12 ; 328 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B12 ; 328 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B13 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; B13 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; B14 ; 302 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B14 ; 302 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B15 ; 304 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B15 ; 304 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B16 ; ; 7A ; VREFB7AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
; B16 ; ; 7A ; VREFB7AN0 ; power ; ; ; -- ; ; -- ; -- ;
|
||||||
@@ -617,7 +642,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B20 ; 278 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B21 ; 276 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B22 ; 272 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B23 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; B23 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; B24 ; 267 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; B25 ; 247 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; B26 ; 249 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -636,7 +661,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; C13 ; 336 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C13 ; 336 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; C14 ; 307 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C14 ; 307 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; C15 ; 306 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C15 ; 306 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; C16 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; C16 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C17 ; 296 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C18 ; 286 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; C19 ; 284 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -665,7 +690,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; D16 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; D16 ; 317 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; D17 ; 293 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; D17 ; 293 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; D18 ; 291 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; D18 ; 291 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; D19 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; D19 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; D20 ; 277 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; D20 ; 277 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; D21 ; 275 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; D21 ; 275 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; D22 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; D22 ; 255 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -684,7 +709,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; E9 ; 374 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; E10 ; 324 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; E11 ; 326 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; E12 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; E12 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; E13 ; 339 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; E14 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; E15 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; E15 ; 325 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -705,7 +730,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; F4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
|
; F5 ; 398 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
|
||||||
; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; F6 ; 360 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; F7 ; 366 ; 8A ; segments[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; F7 ; 366 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
; F8 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
|
||||||
; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; F9 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
@@ -713,7 +738,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; F12 ; 333 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; F13 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
; F14 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
|
||||||
; F15 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; F15 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; F16 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; F16 ; 323 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; F17 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; F17 ; ; 7A, 8A ; VCCPD7A8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; F18 ; 301 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; F18 ; 301 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -736,13 +761,13 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; G9 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G10 ; 357 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G11 ; 329 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G11 ; 329 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G12 ; 331 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G12 ; 331 ; 7A ; seg_a[0] ; output ; 1.2 V ; ; Column I/O ; N ; no ; Off ;
|
||||||
; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; G14 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G14 ; 313 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G15 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G15 ; 311 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G16 ; 279 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G16 ; 279 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G17 ; 281 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; G17 ; 281 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; G18 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; G18 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; G19 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; G19 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; G20 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; G20 ; 258 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; G21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
@@ -761,7 +786,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H8 ; 347 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H9 ; 349 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H10 ; 355 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; H11 ; ; 7A ; VCCIO7A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; H11 ; ; 7A ; VCCIO7A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H12 ; 327 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H13 ; 297 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; H14 ; 295 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -992,7 +1017,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
; U5 ; ; -- ; VCCE_GXBL ; power ; ; 1.1V ; -- ; ; -- ; -- ;
|
||||||
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
; U6 ; 31 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
|
||||||
; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U7 ; 39 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; U8 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U9 ; 54 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U10 ; 81 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U11 ; 79 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
@@ -1002,7 +1027,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U15 ; 148 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; U17 ; 130 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; U18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; U18 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; U19 ; 167 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; U20 ; 181 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; U21 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
@@ -1020,16 +1045,16 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
; V7 ; 28 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
|
||||||
; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V8 ; 41 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V9 ; 70 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V10 ; 72 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V10 ; 72 ; 3B ; b[2] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; V11 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; V11 ; ; 3B ; VCCIO3B ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V12 ; 98 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V13 ; 92 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V14 ; 106 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; V15 ; 124 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; V17 ; 154 ; 4A ; segments[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; V17 ; 154 ; 4A ; seg_a[3] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; V18 ; 156 ; 4A ; segments[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; V18 ; 156 ; 4A ; seg_a[2] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; V19 ; 164 ; 4A ; segments[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; V19 ; 164 ; 4A ; seg_a[1] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; V20 ; 169 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; V21 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; V22 ; 175 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -1047,14 +1072,14 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W8 ; 42 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W10 ; 69 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W11 ; 57 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W11 ; 57 ; 3B ; b[0] ; input ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W12 ; 97 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W13 ; 90 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W14 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; W14 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W15 ; 122 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; W17 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; W18 ; 162 ; 4A ; segments[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; W18 ; 162 ; 4A ; seg_a[4] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; W20 ; 171 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; W21 ; 173 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -1079,10 +1104,10 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; Y14 ; 89 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; Y15 ; 116 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
; Y16 ; 114 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
||||||
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; Y17 ; ; 4A ; VCCIO4A ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
||||||
; Y18 ; 153 ; 4A ; segments[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; Y18 ; 153 ; 4A ; seg_a[7] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; Y19 ; 159 ; 4A ; segments[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; Y19 ; 159 ; 4A ; seg_a[6] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; Y20 ; 161 ; 4A ; segments[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
|
; Y20 ; 161 ; 4A ; seg_a[5] ; output ; 1.2 V ; ; Column I/O ; Y ; no ; Off ;
|
||||||
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
; Y21 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
||||||
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
; Y22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||||
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
; Y23 ; 178 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
||||||
@@ -1093,108 +1118,150 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu
|
|||||||
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------+
|
+-------------------------------------------------+
|
||||||
; I/O Assignment Warnings ;
|
; I/O Assignment Warnings ;
|
||||||
+-------------+-------------------------------+
|
+----------+--------------------------------------+
|
||||||
; Pin Name ; Reason ;
|
; Pin Name ; Reason ;
|
||||||
+-------------+-------------------------------+
|
+----------+--------------------------------------+
|
||||||
; segments[0] ; Incomplete set of assignments ;
|
; seg_b[0] ; Missing drive strength and slew rate ;
|
||||||
; segments[1] ; Incomplete set of assignments ;
|
; seg_b[1] ; Missing drive strength and slew rate ;
|
||||||
; segments[2] ; Incomplete set of assignments ;
|
; seg_b[2] ; Missing drive strength and slew rate ;
|
||||||
; segments[3] ; Incomplete set of assignments ;
|
; seg_b[3] ; Missing drive strength and slew rate ;
|
||||||
; segments[4] ; Incomplete set of assignments ;
|
; seg_b[4] ; Missing drive strength and slew rate ;
|
||||||
; segments[5] ; Incomplete set of assignments ;
|
; seg_b[5] ; Missing drive strength and slew rate ;
|
||||||
; segments[6] ; Incomplete set of assignments ;
|
; seg_b[6] ; Missing drive strength and slew rate ;
|
||||||
; segments[7] ; Incomplete set of assignments ;
|
; seg_b[7] ; Missing drive strength and slew rate ;
|
||||||
; num[0] ; Incomplete set of assignments ;
|
; seg_a[0] ; Missing drive strength and slew rate ;
|
||||||
; rbi_inv[0] ; Incomplete set of assignments ;
|
; seg_a[1] ; Missing drive strength and slew rate ;
|
||||||
; num[3] ; Incomplete set of assignments ;
|
; seg_a[2] ; Missing drive strength and slew rate ;
|
||||||
; num[1] ; Incomplete set of assignments ;
|
; seg_a[3] ; Missing drive strength and slew rate ;
|
||||||
; num[2] ; Incomplete set of assignments ;
|
; seg_a[4] ; Missing drive strength and slew rate ;
|
||||||
+-------------+-------------------------------+
|
; seg_a[5] ; Missing drive strength and slew rate ;
|
||||||
|
; seg_a[6] ; Missing drive strength and slew rate ;
|
||||||
|
; seg_a[7] ; Missing drive strength and slew rate ;
|
||||||
|
; seg_b[0] ; Missing location assignment ;
|
||||||
|
; seg_a[0] ; Missing location assignment ;
|
||||||
|
+----------+--------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Fitter Resource Utilization by Entity ;
|
; Fitter Resource Utilization by Entity ;
|
||||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
; |seven_seg ; 4.5 (4.5) ; 8.0 (8.0) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 13 ; 0 ; |seven_seg ; seven_seg ; work ;
|
; |seven_seg_2digit ; 8.0 (0.5) ; 8.0 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 24 ; 0 ; |seven_seg_2digit ; seven_seg_2digit ; work ;
|
||||||
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------+-------------+--------------+
|
; |seven_seg:left_digit| ; 4.0 (4.0) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:left_digit ; seven_seg ; work ;
|
||||||
|
; |seven_seg:right_digit| ; 3.5 (3.5) ; 3.5 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:right_digit ; seven_seg ; work ;
|
||||||
|
+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Delay Chain Summary ;
|
; Delay Chain Summary ;
|
||||||
+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||||
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
||||||
+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||||
; segments[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; segments[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; seg_b[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; num[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; seg_a[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; rbi_inv[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; seg_a[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; num[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; seg_a[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; num[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; seg_a[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
; num[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; seg_a[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
; seg_a[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
|
; seg_a[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
|
; seg_a[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
||||||
|
; b[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; b[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; b[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; b[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; a[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; a[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; a[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
; a[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
||||||
|
+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------+
|
+----------------------------------------------------------------------+
|
||||||
; Pad To Core Delay Chain Fanout ;
|
; Pad To Core Delay Chain Fanout ;
|
||||||
+---------------------+-------------------+---------+
|
+----------------------------------------+-------------------+---------+
|
||||||
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
||||||
+---------------------+-------------------+---------+
|
+----------------------------------------+-------------------+---------+
|
||||||
; num[0] ; ; ;
|
; b[0] ; ; ;
|
||||||
; - segments~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Decoder0~0 ; 1 ; 0 ;
|
||||||
; - Mux5~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux5~0 ; 1 ; 0 ;
|
||||||
; - Mux4~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux4~0 ; 1 ; 0 ;
|
||||||
; - Mux3~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux3~0 ; 1 ; 0 ;
|
||||||
; - Mux2~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux2~0 ; 1 ; 0 ;
|
||||||
; - Mux1~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux1~0 ; 1 ; 0 ;
|
||||||
; - Mux0~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux0~0 ; 1 ; 0 ;
|
||||||
; - WideOr0~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|WideOr0~0 ; 1 ; 0 ;
|
||||||
; rbi_inv[0] ; ; ;
|
; b[1] ; ; ;
|
||||||
; - segments~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Decoder0~0 ; 0 ; 0 ;
|
||||||
; - Mux5~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux5~0 ; 0 ; 0 ;
|
||||||
; - Mux4~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux4~0 ; 0 ; 0 ;
|
||||||
; - Mux3~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux3~0 ; 0 ; 0 ;
|
||||||
; - Mux2~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux2~0 ; 0 ; 0 ;
|
||||||
; - Mux1~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux1~0 ; 0 ; 0 ;
|
||||||
; - Mux0~0 ; 0 ; 0 ;
|
; - seven_seg:left_digit|Mux0~0 ; 0 ; 0 ;
|
||||||
; num[3] ; ; ;
|
; - seven_seg:left_digit|WideOr0~0 ; 0 ; 0 ;
|
||||||
; - segments~0 ; 1 ; 0 ;
|
; b[2] ; ; ;
|
||||||
; - Mux5~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Decoder0~0 ; 0 ; 0 ;
|
||||||
; - Mux4~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux5~0 ; 0 ; 0 ;
|
||||||
; - Mux3~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux4~0 ; 0 ; 0 ;
|
||||||
; - Mux2~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux3~0 ; 0 ; 0 ;
|
||||||
; - Mux1~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux2~0 ; 0 ; 0 ;
|
||||||
; - Mux0~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux1~0 ; 0 ; 0 ;
|
||||||
; - WideOr0~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux0~0 ; 0 ; 0 ;
|
||||||
; num[1] ; ; ;
|
; - seven_seg:left_digit|WideOr0~0 ; 0 ; 0 ;
|
||||||
; - segments~0 ; 1 ; 0 ;
|
; b[3] ; ; ;
|
||||||
; - Mux5~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Decoder0~0 ; 1 ; 0 ;
|
||||||
; - Mux4~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux5~0 ; 1 ; 0 ;
|
||||||
; - Mux3~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux4~0 ; 1 ; 0 ;
|
||||||
; - Mux2~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux3~0 ; 1 ; 0 ;
|
||||||
; - Mux1~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux2~0 ; 1 ; 0 ;
|
||||||
; - Mux0~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux1~0 ; 1 ; 0 ;
|
||||||
; - WideOr0~0 ; 1 ; 0 ;
|
; - seven_seg:left_digit|Mux0~0 ; 1 ; 0 ;
|
||||||
; num[2] ; ; ;
|
; - seven_seg:left_digit|WideOr0~0 ; 1 ; 0 ;
|
||||||
; - segments~0 ; 1 ; 0 ;
|
; a[0] ; ; ;
|
||||||
; - Mux5~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux5~0 ; 0 ; 0 ;
|
||||||
; - Mux4~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux4~0 ; 0 ; 0 ;
|
||||||
; - Mux3~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux3~0 ; 0 ; 0 ;
|
||||||
; - Mux2~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux2~0 ; 0 ; 0 ;
|
||||||
; - Mux1~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux1~0 ; 0 ; 0 ;
|
||||||
; - Mux0~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|Mux0~0 ; 0 ; 0 ;
|
||||||
; - WideOr0~0 ; 1 ; 0 ;
|
; - seven_seg:right_digit|WideOr0~0 ; 0 ; 0 ;
|
||||||
+---------------------+-------------------+---------+
|
; a[1] ; ; ;
|
||||||
|
; - seven_seg:right_digit|Mux5~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux4~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux3~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux2~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux1~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux0~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|WideOr0~0 ; 1 ; 0 ;
|
||||||
|
; a[2] ; ; ;
|
||||||
|
; - seven_seg:right_digit|Mux5~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux4~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux3~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux2~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux1~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux0~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|WideOr0~0 ; 1 ; 0 ;
|
||||||
|
; a[3] ; ; ;
|
||||||
|
; - seven_seg:right_digit|Mux5~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux4~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux3~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux2~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux1~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|Mux0~0 ; 1 ; 0 ;
|
||||||
|
; - seven_seg:right_digit|WideOr0~0 ; 1 ; 0 ;
|
||||||
|
+----------------------------------------+-------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------+
|
+-------------------------------------------------------+
|
||||||
@@ -1202,10 +1269,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
+------------------------------+------------------------+
|
+------------------------------+------------------------+
|
||||||
; Routing Resource Type ; Usage ;
|
; Routing Resource Type ; Usage ;
|
||||||
+------------------------------+------------------------+
|
+------------------------------+------------------------+
|
||||||
; Block interconnects ; 13 / 217,884 ( < 1 % ) ;
|
; Block interconnects ; 23 / 217,884 ( < 1 % ) ;
|
||||||
; C12 interconnects ; 0 / 10,080 ( 0 % ) ;
|
; C12 interconnects ; 4 / 10,080 ( < 1 % ) ;
|
||||||
; C2 interconnects ; 10 / 87,208 ( < 1 % ) ;
|
; C2 interconnects ; 14 / 87,208 ( < 1 % ) ;
|
||||||
; C4 interconnects ; 17 / 41,360 ( < 1 % ) ;
|
; C4 interconnects ; 7 / 41,360 ( < 1 % ) ;
|
||||||
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
; DQS bus muxes ; 0 / 21 ( 0 % ) ;
|
||||||
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||||
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ;
|
||||||
@@ -1214,10 +1281,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
||||||
; Local interconnects ; 0 / 58,160 ( 0 % ) ;
|
; Local interconnects ; 0 / 58,160 ( 0 % ) ;
|
||||||
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
; Quadrant clocks ; 0 / 88 ( 0 % ) ;
|
||||||
; R14 interconnects ; 10 / 9,228 ( < 1 % ) ;
|
; R14 interconnects ; 19 / 9,228 ( < 1 % ) ;
|
||||||
; R14/C12 interconnect drivers ; 10 / 15,096 ( < 1 % ) ;
|
; R14/C12 interconnect drivers ; 19 / 15,096 ( < 1 % ) ;
|
||||||
; R3 interconnects ; 13 / 94,896 ( < 1 % ) ;
|
; R3 interconnects ; 27 / 94,896 ( < 1 % ) ;
|
||||||
; R6 interconnects ; 19 / 194,640 ( < 1 % ) ;
|
; R6 interconnects ; 14 / 194,640 ( < 1 % ) ;
|
||||||
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
; Spine clocks ; 0 / 180 ( 0 % ) ;
|
||||||
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
; Wire stub REs ; 0 / 11,606 ( 0 % ) ;
|
||||||
+------------------------------+------------------------+
|
+------------------------------+------------------------+
|
||||||
@@ -1273,29 +1340,40 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; I/O Rules Matrix ;
|
; I/O Rules Matrix ;
|
||||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||||
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
||||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||||
; Total Pass ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 13 ; 13 ; 0 ;
|
; Total Pass ; 0 ; 22 ; 22 ; 0 ; 0 ; 24 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 16 ; 0 ; 24 ; 24 ; 0 ;
|
||||||
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
; Total Inapplicable ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 5 ; 13 ; 13 ; 13 ; 13 ; 5 ; 13 ; 13 ; 13 ; 13 ; 5 ; 13 ; 0 ; 0 ; 13 ;
|
; Total Inapplicable ; 24 ; 2 ; 2 ; 24 ; 24 ; 0 ; 2 ; 24 ; 24 ; 24 ; 24 ; 24 ; 24 ; 8 ; 24 ; 24 ; 24 ; 24 ; 8 ; 24 ; 24 ; 24 ; 24 ; 8 ; 24 ; 0 ; 0 ; 24 ;
|
||||||
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||||
; segments[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; segments[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_b[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; num[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_a[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; rbi_inv[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_a[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; num[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_a[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; num[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_a[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
; num[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; seg_a[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
; seg_a[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; seg_a[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; seg_a[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; b[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; b[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; b[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; b[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; a[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; a[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; a[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
; a[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
||||||
|
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------+
|
||||||
@@ -1352,11 +1430,14 @@ Info (21077): High junction temperature is 85 degrees C
|
|||||||
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
|
||||||
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
|
||||||
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
||||||
|
Critical Warning (169085): No exact pin location assignment(s) for 2 pins of 24 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
|
||||||
Info (184020): Starting Fitter periphery placement operations
|
Info (184020): Starting Fitter periphery placement operations
|
||||||
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
|
||||||
Info (176233): Starting register packing
|
Info (176233): Starting register packing
|
||||||
Info (176235): Finished register packing
|
Info (176235): Finished register packing
|
||||||
Extra Info (176219): No registers were packed into other blocks
|
Extra Info (176219): No registers were packed into other blocks
|
||||||
|
Warning (15705): Ignored locations or region assignments to the following nodes
|
||||||
|
Warning (15706): Node "rbi[0]" is assigned to location or region, but does not exist in design
|
||||||
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
|
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:07
|
||||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||||
Info (332144): No user constrained base clocks found in the design
|
Info (332144): No user constrained base clocks found in the design
|
||||||
@@ -1373,7 +1454,7 @@ Info (170137): Fitter placement was successful
|
|||||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
|
||||||
Info (170193): Fitter routing operations beginning
|
Info (170193): Fitter routing operations beginning
|
||||||
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
|
||||||
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11
|
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11
|
||||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||||
Info (170200): Optimizations that may affect the design's timing were skipped
|
Info (170200): Optimizations that may affect the design's timing were skipped
|
||||||
@@ -1384,10 +1465,11 @@ Info (334004): Delay annotation completed successfully
|
|||||||
Info (334003): Started post-fitting delay annotation
|
Info (334003): Started post-fitting delay annotation
|
||||||
Info (334004): Delay annotation completed successfully
|
Info (334004): Delay annotation completed successfully
|
||||||
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
|
||||||
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||||
Info: Peak virtual memory: 1384 megabytes
|
Info: Quartus Prime Fitter was successful. 0 errors, 9 warnings
|
||||||
Info: Processing ended: Tue Sep 15 16:10:15 2026
|
Info: Peak virtual memory: 1392 megabytes
|
||||||
|
Info: Processing ended: Tue Sep 15 21:07:03 2026
|
||||||
Info: Elapsed time: 00:00:29
|
Info: Elapsed time: 00:00:29
|
||||||
Info: Total CPU time (on all processors): 00:00:40
|
Info: Total CPU time (on all processors): 00:00:41
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,6 @@
|
|||||||
|
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||||
|
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||||
|
Extra Info (176238): Start inferring scan chains for DSP blocks
|
||||||
|
Extra Info (176239): Inferring scan chains for DSP blocks is complete
|
||||||
|
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
|
||||||
|
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
|
||||||
@@ -1,13 +1,13 @@
|
|||||||
Fitter Status : Successful - Tue Sep 15 16:10:14 2026
|
Fitter Status : Successful - Tue Sep 15 21:07:03 2026
|
||||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Revision Name : seven_seg
|
Revision Name : seven_seg
|
||||||
Top-level Entity Name : seven_seg
|
Top-level Entity Name : seven_seg_2digit
|
||||||
Family : Cyclone V
|
Family : Cyclone V
|
||||||
Device : 5CGXFC5C6F27C7
|
Device : 5CGXFC5C6F27C7
|
||||||
Timing Models : Final
|
Timing Models : Final
|
||||||
Logic utilization (in ALMs) : 5 / 29,080 ( < 1 % )
|
Logic utilization (in ALMs) : 8 / 29,080 ( < 1 % )
|
||||||
Total registers : 0
|
Total registers : 0
|
||||||
Total pins : 13 / 364 ( 4 % )
|
Total pins : 24 / 364 ( 7 % )
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
Total block memory bits : 0 / 4,567,040 ( 0 % )
|
Total block memory bits : 0 / 4,567,040 ( 0 % )
|
||||||
Total RAM Blocks : 0 / 446 ( 0 % )
|
Total RAM Blocks : 0 / 446 ( 0 % )
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
Flow report for seven_seg
|
Flow report for seven_seg
|
||||||
Tue Sep 15 16:10:32 2026
|
Tue Sep 15 21:07:19 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -41,16 +41,16 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Flow Status ; Successful - Tue Sep 15 16:10:32 2026 ;
|
; Flow Status ; Successful - Tue Sep 15 21:07:19 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
; Top-level Entity Name ; seven_seg ;
|
; Top-level Entity Name ; seven_seg_2digit ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
; Device ; 5CGXFC5C6F27C7 ;
|
; Device ; 5CGXFC5C6F27C7 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Logic utilization (in ALMs) ; 5 / 29,080 ( < 1 % ) ;
|
; Logic utilization (in ALMs) ; 8 / 29,080 ( < 1 % ) ;
|
||||||
; Total registers ; 0 ;
|
; Total registers ; 0 ;
|
||||||
; Total pins ; 13 / 364 ( 4 % ) ;
|
; Total pins ; 24 / 364 ( 7 % ) ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
; Total block memory bits ; 0 / 4,567,040 ( 0 % ) ;
|
||||||
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
|
; Total DSP Blocks ; 0 / 150 ( 0 % ) ;
|
||||||
@@ -68,32 +68,35 @@ on the Quartus Prime software download page.
|
|||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 09/15/2026 16:09:34 ;
|
; Start date & time ; 09/15/2026 21:06:22 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Non-Default Global Settings ;
|
; Flow Non-Default Global Settings ;
|
||||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
|
||||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
|
||||||
; COMPILER_SIGNATURE_ID ; 268883478169649.178945257408043 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 268883478169649.178947038213924 ; -- ; -- ; -- ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
|
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
|
||||||
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
|
; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
|
||||||
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
|
; EDA_SIMULATION_TOOL ; Questa Altera FPGA (SystemVerilog) ; <None> ; -- ; -- ;
|
||||||
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
||||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
|
||||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
|
||||||
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; seven_seg_2digit ; Top ;
|
||||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
||||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
||||||
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
|
; TOP_LEVEL_ENTITY ; seven_seg_2digit ; seven_seg ; -- ; -- ;
|
||||||
|
+-------------------------------------+----------------------------------------+---------------+------------------+-----------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------+
|
||||||
@@ -101,12 +104,12 @@ on the Quartus Prime software download page.
|
|||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:24 ;
|
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 422 MB ; 00:00:24 ;
|
||||||
; Fitter ; 00:00:28 ; 1.0 ; 1384 MB ; 00:00:40 ;
|
; Fitter ; 00:00:29 ; 1.0 ; 1392 MB ; 00:00:41 ;
|
||||||
; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ;
|
; Assembler ; 00:00:05 ; 1.0 ; 514 MB ; 00:00:05 ;
|
||||||
; Timing Analyzer ; 00:00:05 ; 1.0 ; 788 MB ; 00:00:06 ;
|
; Timing Analyzer ; 00:00:06 ; 1.0 ; 769 MB ; 00:00:06 ;
|
||||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ;
|
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 670 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ;
|
; Total ; 00:00:51 ; -- ; -- ; 00:01:17 ;
|
||||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
Analysis & Synthesis report for seven_seg
|
Analysis & Synthesis report for seven_seg
|
||||||
Tue Sep 15 16:09:45 2026
|
Tue Sep 15 21:06:33 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -14,10 +14,11 @@ Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
|||||||
6. Analysis & Synthesis Resource Usage Summary
|
6. Analysis & Synthesis Resource Usage Summary
|
||||||
7. Analysis & Synthesis Resource Utilization by Entity
|
7. Analysis & Synthesis Resource Utilization by Entity
|
||||||
8. General Register Statistics
|
8. General Register Statistics
|
||||||
9. Multiplexer Restructuring Statistics (Restructuring Performed)
|
9. Port Connectivity Checks: "seven_seg:right_digit"
|
||||||
10. Post-Synthesis Netlist Statistics for Top Partition
|
10. Port Connectivity Checks: "seven_seg:left_digit"
|
||||||
11. Elapsed Time Per Partition
|
11. Post-Synthesis Netlist Statistics for Top Partition
|
||||||
12. Analysis & Synthesis Messages
|
12. Elapsed Time Per Partition
|
||||||
|
13. Analysis & Synthesis Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -44,14 +45,14 @@ on the Quartus Prime software download page.
|
|||||||
+-----------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+---------------------------------+-------------------------------------------------+
|
+---------------------------------+-------------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Tue Sep 15 16:09:45 2026 ;
|
; Analysis & Synthesis Status ; Successful - Tue Sep 15 21:06:33 2026 ;
|
||||||
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
|
||||||
; Revision Name ; seven_seg ;
|
; Revision Name ; seven_seg ;
|
||||||
; Top-level Entity Name ; seven_seg ;
|
; Top-level Entity Name ; seven_seg_2digit ;
|
||||||
; Family ; Cyclone V ;
|
; Family ; Cyclone V ;
|
||||||
; Logic utilization (in ALMs) ; N/A ;
|
; Logic utilization (in ALMs) ; N/A ;
|
||||||
; Total registers ; 0 ;
|
; Total registers ; 0 ;
|
||||||
; Total pins ; 13 ;
|
; Total pins ; 24 ;
|
||||||
; Total virtual pins ; 0 ;
|
; Total virtual pins ; 0 ;
|
||||||
; Total block memory bits ; 0 ;
|
; Total block memory bits ; 0 ;
|
||||||
; Total DSP Blocks ; 0 ;
|
; Total DSP Blocks ; 0 ;
|
||||||
@@ -70,7 +71,7 @@ on the Quartus Prime software download page.
|
|||||||
; Option ; Setting ; Default Value ;
|
; Option ; Setting ; Default Value ;
|
||||||
+---------------------------------------------------------------------------------+--------------------+--------------------+
|
+---------------------------------------------------------------------------------+--------------------+--------------------+
|
||||||
; Device ; 5CGXFC5C6F27C7 ; ;
|
; Device ; 5CGXFC5C6F27C7 ; ;
|
||||||
; Top-level entity name ; seven_seg ; seven_seg ;
|
; Top-level entity name ; seven_seg_2digit ; seven_seg ;
|
||||||
; Family name ; Cyclone V ; Cyclone V ;
|
; Family name ; Cyclone V ; Cyclone V ;
|
||||||
; Use smart compilation ; Off ; Off ;
|
; Use smart compilation ; Off ; Off ;
|
||||||
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||||
@@ -176,40 +177,42 @@ on the Quartus Prime software download page.
|
|||||||
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------+
|
+----------------------------------------------------------+
|
||||||
; Analysis & Synthesis Resource Usage Summary ;
|
; Analysis & Synthesis Resource Usage Summary ;
|
||||||
+---------------------------------------------+--------------+
|
+---------------------------------------------+------------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+---------------------------------------------+--------------+
|
+---------------------------------------------+------------+
|
||||||
; Estimate of Logic utilization (ALMs needed) ; 4 ;
|
; Estimate of Logic utilization (ALMs needed) ; 8 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Combinational ALUT usage for logic ; 8 ;
|
; Combinational ALUT usage for logic ; 15 ;
|
||||||
; -- 7 input functions ; 0 ;
|
; -- 7 input functions ; 0 ;
|
||||||
; -- 6 input functions ; 0 ;
|
; -- 6 input functions ; 0 ;
|
||||||
; -- 5 input functions ; 7 ;
|
; -- 5 input functions ; 0 ;
|
||||||
; -- 4 input functions ; 1 ;
|
; -- 4 input functions ; 15 ;
|
||||||
; -- <=3 input functions ; 0 ;
|
; -- <=3 input functions ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Dedicated logic registers ; 0 ;
|
; Dedicated logic registers ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; I/O pins ; 13 ;
|
; I/O pins ; 24 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Total DSP Blocks ; 0 ;
|
; Total DSP Blocks ; 0 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Maximum fan-out node ; num[0]~input ;
|
; Maximum fan-out node ; b[0]~input ;
|
||||||
; Maximum fan-out ; 8 ;
|
; Maximum fan-out ; 8 ;
|
||||||
; Total fan-out ; 60 ;
|
; Total fan-out ; 99 ;
|
||||||
; Average fan-out ; 1.76 ;
|
; Average fan-out ; 1.57 ;
|
||||||
+---------------------------------------------+--------------+
|
+---------------------------------------------+------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
; |seven_seg ; 8 (8) ; 0 (0) ; 0 ; 0 ; 13 ; 0 ; |seven_seg ; seven_seg ; work ;
|
; |seven_seg_2digit ; 15 (0) ; 0 (0) ; 0 ; 0 ; 24 ; 0 ; |seven_seg_2digit ; seven_seg_2digit ; work ;
|
||||||
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+---------------------+-------------+--------------+
|
; |seven_seg:left_digit| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:left_digit ; seven_seg ; work ;
|
||||||
|
; |seven_seg:right_digit| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |seven_seg_2digit|seven_seg:right_digit ; seven_seg ; work ;
|
||||||
|
+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------+------------------+--------------+
|
||||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||||
|
|
||||||
|
|
||||||
@@ -228,13 +231,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
+----------------------------------------------+-------+
|
+----------------------------------------------+-------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------+
|
||||||
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
; Port Connectivity Checks: "seven_seg:right_digit" ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+---------+-------+----------+----------------------+
|
||||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
; Port ; Type ; Severity ; Details ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+---------+-------+----------+----------------------+
|
||||||
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |seven_seg|Mux3 ;
|
; rbi_inv ; Input ; Info ; Stuck at VCC ;
|
||||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
+---------+-------+----------+----------------------+
|
||||||
|
|
||||||
|
|
||||||
|
+--------------------------------------------------+
|
||||||
|
; Port Connectivity Checks: "seven_seg:left_digit" ;
|
||||||
|
+---------+-------+----------+---------------------+
|
||||||
|
; Port ; Type ; Severity ; Details ;
|
||||||
|
+---------+-------+----------+---------------------+
|
||||||
|
; rbi_inv ; Input ; Info ; Stuck at GND ;
|
||||||
|
+---------+-------+----------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------+
|
+-----------------------------------------------------+
|
||||||
@@ -242,15 +254,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
+-----------------------+-----------------------------+
|
+-----------------------+-----------------------------+
|
||||||
; Type ; Count ;
|
; Type ; Count ;
|
||||||
+-----------------------+-----------------------------+
|
+-----------------------+-----------------------------+
|
||||||
; arriav_lcell_comb ; 10 ;
|
; arriav_lcell_comb ; 24 ;
|
||||||
; normal ; 10 ;
|
; normal ; 24 ;
|
||||||
; 1 data inputs ; 2 ;
|
; 0 data inputs ; 1 ;
|
||||||
; 4 data inputs ; 1 ;
|
; 1 data inputs ; 8 ;
|
||||||
; 5 data inputs ; 7 ;
|
; 4 data inputs ; 15 ;
|
||||||
; boundary_port ; 13 ;
|
; boundary_port ; 24 ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Max LUT depth ; 2.00 ;
|
; Max LUT depth ; 2.00 ;
|
||||||
; Average LUT depth ; 1.60 ;
|
; Average LUT depth ; 1.72 ;
|
||||||
+-----------------------+-----------------------------+
|
+-----------------------+-----------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -269,24 +281,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Analysis & Synthesis
|
Info: Running Quartus Prime Analysis & Synthesis
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 15 16:09:33 2026
|
Info: Processing started: Tue Sep 15 21:06:22 2026
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
||||||
Info (12021): Found 1 design units, including 1 entities, in source file seven_seg.sv
|
Info (12021): Found 2 design units, including 2 entities, in source file seven_seg.sv
|
||||||
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 3
|
Info (12023): Found entity 1: seven_seg File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 4
|
||||||
Info (12127): Elaborating entity "seven_seg" for the top level hierarchy
|
Info (12023): Found entity 2: seven_seg_2digit File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 32
|
||||||
|
Info (12127): Elaborating entity "seven_seg_2digit" for the top level hierarchy
|
||||||
|
Info (12128): Elaborating entity "seven_seg" for hierarchy "seven_seg:left_digit" File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 45
|
||||||
|
Warning (13024): Output pins are stuck at VCC or GND
|
||||||
|
Warning (13410): Pin "seg_a[0]" is stuck at GND File: /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv Line: 36
|
||||||
Info (286030): Timing-Driven Synthesis is running
|
Info (286030): Timing-Driven Synthesis is running
|
||||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||||
Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
|
Info (21057): Implemented 39 device resources after synthesis - the final resource count might be different
|
||||||
Info (21058): Implemented 5 input pins
|
Info (21058): Implemented 8 input pins
|
||||||
Info (21059): Implemented 8 output pins
|
Info (21059): Implemented 16 output pins
|
||||||
Info (21061): Implemented 8 logic cells
|
Info (21061): Implemented 15 logic cells
|
||||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings
|
||||||
Info: Peak virtual memory: 436 megabytes
|
Info: Peak virtual memory: 439 megabytes
|
||||||
Info: Processing ended: Tue Sep 15 16:09:45 2026
|
Info: Processing ended: Tue Sep 15 21:06:33 2026
|
||||||
Info: Elapsed time: 00:00:12
|
Info: Elapsed time: 00:00:11
|
||||||
Info: Total CPU time (on all processors): 00:00:24
|
Info: Total CPU time (on all processors): 00:00:25
|
||||||
|
|
||||||
|
|
||||||
@@ -1,11 +1,11 @@
|
|||||||
Analysis & Synthesis Status : Successful - Tue Sep 15 16:09:45 2026
|
Analysis & Synthesis Status : Successful - Tue Sep 15 21:06:33 2026
|
||||||
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Revision Name : seven_seg
|
Revision Name : seven_seg
|
||||||
Top-level Entity Name : seven_seg
|
Top-level Entity Name : seven_seg_2digit
|
||||||
Family : Cyclone V
|
Family : Cyclone V
|
||||||
Logic utilization (in ALMs) : N/A
|
Logic utilization (in ALMs) : N/A
|
||||||
Total registers : 0
|
Total registers : 0
|
||||||
Total pins : 13
|
Total pins : 24
|
||||||
Total virtual pins : 0
|
Total virtual pins : 0
|
||||||
Total block memory bits : 0
|
Total block memory bits : 0
|
||||||
Total DSP Blocks : 0
|
Total DSP Blocks : 0
|
||||||
|
|||||||
@@ -29,12 +29,12 @@
|
|||||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||||
-- of its bank.
|
-- of its bank.
|
||||||
-- Bank 3A: 2.5V
|
-- Bank 3A: 2.5V
|
||||||
-- Bank 3B: 2.5V
|
-- Bank 3B: 1.2V
|
||||||
-- Bank 4A: 2.5V
|
-- Bank 4A: 1.2V
|
||||||
-- Bank 5A: 2.5V
|
-- Bank 5A: 2.5V
|
||||||
-- Bank 5B: 2.5V
|
-- Bank 5B: 2.5V
|
||||||
-- Bank 6A: 2.5V
|
-- Bank 6A: 2.5V
|
||||||
-- Bank 7A: 2.5V
|
-- Bank 7A: 1.2V
|
||||||
-- Bank 8A: 2.5V
|
-- Bank 8A: 2.5V
|
||||||
-- Bank 9A: Dedicated configuration pins only, no VCCIO required.
|
-- Bank 9A: Dedicated configuration pins only, no VCCIO required.
|
||||||
-- RREF : External reference resistor for the quad, MUST be connected to
|
-- RREF : External reference resistor for the quad, MUST be connected to
|
||||||
@@ -84,7 +84,7 @@ CONF_DONE : A6 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7A :
|
||||||
VCCIO7A : A10 : power : : 2.5V : 7A :
|
VCCIO7A : A10 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7A :
|
||||||
@@ -94,7 +94,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7A :
|
||||||
VCCIO7A : A20 : power : : 2.5V : 7A :
|
VCCIO7A : A20 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
|
||||||
@@ -109,7 +109,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 3A :
|
||||||
VCC_AUX : AA8 : power : : 2.5V : :
|
VCC_AUX : AA8 : power : : 2.5V : :
|
||||||
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
VCCPGM : AA9 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||||
VCCIO3B : AA10 : power : : 2.5V : 3B :
|
VCCIO3B : AA10 : power : : 1.2V : 3B :
|
||||||
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
|
VCCPD3B4A : AA11 : power : : 2.5V : 3B, 4A :
|
||||||
NC : AA12 : : : : :
|
NC : AA12 : : : : :
|
||||||
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
|
VCCPD3B4A : AA13 : power : : 2.5V : 3B, 4A :
|
||||||
@@ -117,9 +117,9 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : :
|
|||||||
GND : AA15 : gnd : : : :
|
GND : AA15 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
|
||||||
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
|
VCCPD3B4A : AA17 : power : : 2.5V : 3B, 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
|
seg_b[1] : AA18 : output : 1.2 V : : 4A : Y
|
||||||
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
|
VCCPD3B4A : AA19 : power : : 2.5V : 3B, 4A :
|
||||||
VCCIO4A : AA20 : power : : 2.5V : 4A :
|
VCCIO4A : AA20 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5A :
|
||||||
@@ -135,16 +135,16 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : :
|
|||||||
NC : AB7 : : : : :
|
NC : AB7 : : : : :
|
||||||
GND : AB8 : gnd : : : :
|
GND : AB8 : gnd : : : :
|
||||||
VCCPD3A : AB9 : power : : 2.5V : 3A :
|
VCCPD3A : AB9 : power : : 2.5V : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3B :
|
b[1] : AB10 : input : 1.2 V : : 3B : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3B :
|
||||||
VCCIO4A : AB13 : power : : 2.5V : 4A :
|
VCCIO4A : AB13 : power : : 1.2V : 4A :
|
||||||
VCC_AUX : AB14 : power : : 2.5V : :
|
VCC_AUX : AB14 : power : : 2.5V : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4A :
|
||||||
GND : AB18 : gnd : : : :
|
GND : AB18 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4A :
|
seg_b[3] : AB19 : output : 1.2 V : : 4A : Y
|
||||||
VCC_AUX : AB20 : power : : 2.5V : :
|
VCC_AUX : AB20 : power : : 2.5V : :
|
||||||
VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A :
|
VCCPD3B4A : AB21 : power : : 2.5V : 3B, 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4A :
|
||||||
@@ -159,18 +159,18 @@ GXB_NC : AC4 : : :
|
|||||||
GND : AC5 : gnd : : : :
|
GND : AC5 : gnd : : : :
|
||||||
VCCIO3A : AC6 : power : : 2.5V : 3A :
|
VCCIO3A : AC6 : power : : 2.5V : 3A :
|
||||||
VREFB3AN0 : AC7 : power : : : 3A :
|
VREFB3AN0 : AC7 : power : : : 3A :
|
||||||
num[3] : AC8 : input : 2.5 V : : 3B : Y
|
a[3] : AC8 : input : 1.2 V : : 3B : Y
|
||||||
num[0] : AC9 : input : 2.5 V : : 3B : Y
|
a[0] : AC9 : input : 1.2 V : : 3B : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3B :
|
b[3] : AC10 : input : 1.2 V : : 3B : Y
|
||||||
GND : AC11 : gnd : : : :
|
GND : AC11 : gnd : : : :
|
||||||
VREFB3BN0 : AC12 : power : : : 3B :
|
VREFB3BN0 : AC12 : power : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC13 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4A :
|
||||||
VCCIO4A : AC16 : power : : 2.5V : 4A :
|
VCCIO4A : AC16 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4A :
|
seg_b[6] : AC19 : output : 1.2 V : : 4A : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC20 : : : : 4A :
|
||||||
GND : AC21 : gnd : : : :
|
GND : AC21 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 5A :
|
||||||
@@ -186,24 +186,24 @@ AS_DATA1, DATA1 : AD5 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD6 : : : : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3B :
|
||||||
VCCIO3B : AD9 : power : : 2.5V : 3B :
|
VCCIO3B : AD9 : power : : 1.2V : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 4A :
|
||||||
num[2] : AD13 : input : 2.5 V : : 4A : Y
|
a[2] : AD13 : input : 1.2 V : : 4A : Y
|
||||||
GND : AD14 : gnd : : : :
|
GND : AD14 : gnd : : : :
|
||||||
VREFB4AN0 : AD15 : power : : : 4A :
|
VREFB4AN0 : AD15 : power : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD16 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4A :
|
||||||
VCCIO4A : AD19 : power : : 2.5V : 4A :
|
VCCIO4A : AD19 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD20 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
|
seg_b[0] : AD21 : output : 1.2 V : : 4A : N
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD23 : : : : 4A :
|
||||||
GND : AD24 : gnd : : : :
|
GND : AD24 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 4A :
|
seg_b[2] : AD26 : output : 1.2 V : : 4A : Y
|
||||||
GND : AE1 : gnd : : : :
|
GND : AE1 : gnd : : : :
|
||||||
GND : AE2 : gnd : : : :
|
GND : AE2 : gnd : : : :
|
||||||
GXB_NC : AE3 : : : : B0L :
|
GXB_NC : AE3 : : : : B0L :
|
||||||
@@ -213,23 +213,23 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : :
|
|||||||
GND : AE7 : gnd : : : :
|
GND : AE7 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3B :
|
||||||
num[1] : AE10 : input : 2.5 V : : 4A : Y
|
a[1] : AE10 : input : 1.2 V : : 4A : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 4A :
|
||||||
VCCIO4A : AE12 : power : : 2.5V : 4A :
|
VCCIO4A : AE12 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4A :
|
||||||
GND : AE17 : gnd : : : :
|
GND : AE17 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
|
||||||
rbi_inv[0] : AE19 : input : 2.5 V : : 4A : Y
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4A :
|
||||||
VCCIO4A : AE22 : power : : 2.5V : 4A :
|
VCCIO4A : AE22 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4A :
|
seg_b[5] : AE25 : output : 1.2 V : : 4A : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 4A :
|
seg_b[4] : AE26 : output : 1.2 V : : 4A : Y
|
||||||
GND : AF2 : gnd : : : :
|
GND : AF2 : gnd : : : :
|
||||||
GND : AF3 : gnd : : : :
|
GND : AF3 : gnd : : : :
|
||||||
GND : AF4 : gnd : : : :
|
GND : AF4 : gnd : : : :
|
||||||
@@ -243,7 +243,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 4A :
|
||||||
VCCIO4A : AF15 : power : : 2.5V : 4A :
|
VCCIO4A : AF15 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4A :
|
||||||
@@ -252,7 +252,7 @@ GND : AF20 : gnd : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
|
seg_b[7] : AF24 : output : 1.2 V : : 4A : Y
|
||||||
GND : AF25 : gnd : : : :
|
GND : AF25 : gnd : : : :
|
||||||
RREF : B1 : : : : :
|
RREF : B1 : : : : :
|
||||||
GND : B2 : gnd : : : :
|
GND : B2 : gnd : : : :
|
||||||
@@ -266,7 +266,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7A :
|
||||||
VCCIO7A : B13 : power : : 2.5V : 7A :
|
VCCIO7A : B13 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7A :
|
||||||
VREFB7AN0 : B16 : power : : : 7A :
|
VREFB7AN0 : B16 : power : : : 7A :
|
||||||
@@ -276,7 +276,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
|
||||||
VCCIO7A : B23 : power : : 2.5V : 7A :
|
VCCIO7A : B23 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B24 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 6A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 6A :
|
||||||
@@ -295,7 +295,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7A :
|
||||||
VCCIO7A : C16 : power : : 2.5V : 7A :
|
VCCIO7A : C16 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7A :
|
||||||
@@ -324,7 +324,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7A :
|
||||||
VCCIO7A : D19 : power : : 2.5V : 7A :
|
VCCIO7A : D19 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 6A :
|
||||||
@@ -343,7 +343,7 @@ VCCBAT : E8 : power : : 1.2V
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7A :
|
||||||
VCCIO7A : E12 : power : : 2.5V : 7A :
|
VCCIO7A : E12 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 7A :
|
||||||
VCC_AUX : E14 : power : : 2.5V : :
|
VCC_AUX : E14 : power : : 2.5V : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7A :
|
||||||
@@ -364,7 +364,7 @@ GND : F3 : gnd : :
|
|||||||
GND : F4 : gnd : : : :
|
GND : F4 : gnd : : : :
|
||||||
nCONFIG : F5 : : : : 9A :
|
nCONFIG : F5 : : : : 9A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
|
||||||
segments[0] : F7 : output : 2.5 V : : 8A : Y
|
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8A :
|
||||||
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
VCCPGM : F8 : power : : 1.8V/2.5V/3.0V/3.3V : :
|
||||||
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
|
VCCPD7A8A : F9 : power : : 2.5V : 7A, 8A :
|
||||||
GND : F10 : gnd : : : :
|
GND : F10 : gnd : : : :
|
||||||
@@ -372,7 +372,7 @@ VCCPD7A8A : F11 : power : : 2.5V
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 7A :
|
||||||
VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A :
|
VCCPD7A8A : F13 : power : : 2.5V : 7A, 8A :
|
||||||
DNU : F14 : : : : :
|
DNU : F14 : : : : :
|
||||||
VCCIO7A : F15 : power : : 2.5V : 7A :
|
VCCIO7A : F15 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7A :
|
||||||
VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A :
|
VCCPD7A8A : F17 : power : : 2.5V : 7A, 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7A :
|
||||||
@@ -395,13 +395,13 @@ VCCIO8A : G8 : power : : 2.5V
|
|||||||
VCC_AUX : G9 : power : : 2.5V : :
|
VCC_AUX : G9 : power : : 2.5V : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 7A :
|
seg_a[0] : G12 : output : 1.2 V : : 7A : N
|
||||||
GND : G13 : gnd : : : :
|
GND : G13 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7A :
|
||||||
VCCIO7A : G18 : power : : 2.5V : 7A :
|
VCCIO7A : G18 : power : : 1.2V : 7A :
|
||||||
VCC_AUX : G19 : power : : 2.5V : :
|
VCC_AUX : G19 : power : : 2.5V : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 6A :
|
||||||
VCCA_FPLL : G21 : power : : 2.5V : :
|
VCCA_FPLL : G21 : power : : 2.5V : :
|
||||||
@@ -420,7 +420,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H9 : : : : 8A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8A :
|
||||||
VCCIO7A : H11 : power : : 2.5V : 7A :
|
VCCIO7A : H11 : power : : 1.2V : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 7A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 7A :
|
||||||
@@ -651,7 +651,7 @@ GND : U4 : gnd : :
|
|||||||
VCCE_GXBL : U5 : power : : 1.1V : :
|
VCCE_GXBL : U5 : power : : 1.1V : :
|
||||||
AS_DATA3, DATA3 : U6 : : : : 3A :
|
AS_DATA3, DATA3 : U6 : : : : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3A :
|
||||||
VCCIO3B : U8 : power : : 2.5V : 3B :
|
VCCIO3B : U8 : power : : 1.2V : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U9 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U10 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U11 : : : : 3B :
|
||||||
@@ -661,7 +661,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U15 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4A :
|
||||||
VCCIO4A : U18 : power : : 2.5V : 4A :
|
VCCIO4A : U18 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U19 : : : : 5A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 5A :
|
||||||
VCCPD5A : U21 : power : : 2.5V : 5A :
|
VCCPD5A : U21 : power : : 2.5V : 5A :
|
||||||
@@ -679,16 +679,16 @@ GND : V6 : : :
|
|||||||
TDO : V7 : output : : : 3A :
|
TDO : V7 : output : : : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 3A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V9 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V10 : : : : 3B :
|
b[2] : V10 : input : 1.2 V : : 3B : Y
|
||||||
VCCIO3B : V11 : power : : 2.5V : 3B :
|
VCCIO3B : V11 : power : : 1.2V : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V12 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V13 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V14 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V15 : : : : 4A :
|
||||||
GND : V16 : gnd : : : :
|
GND : V16 : gnd : : : :
|
||||||
segments[3] : V17 : output : 2.5 V : : 4A : Y
|
seg_a[3] : V17 : output : 1.2 V : : 4A : Y
|
||||||
segments[2] : V18 : output : 2.5 V : : 4A : Y
|
seg_a[2] : V18 : output : 1.2 V : : 4A : Y
|
||||||
segments[1] : V19 : output : 2.5 V : : 4A : Y
|
seg_a[1] : V19 : output : 1.2 V : : 4A : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 5A :
|
||||||
VCCIO5A : V21 : power : : 2.5V : 5A :
|
VCCIO5A : V21 : power : : 2.5V : 5A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5A :
|
||||||
@@ -706,14 +706,14 @@ VCCA_FPLL : W7 : power : : 2.5V
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 3A :
|
||||||
GND : W9 : gnd : : : :
|
GND : W9 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W10 : : : : 3B :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W11 : : : : 3B :
|
b[0] : W11 : input : 1.2 V : : 3B : Y
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W12 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W13 : : : : 4A :
|
||||||
VCCIO4A : W14 : power : : 2.5V : 4A :
|
VCCIO4A : W14 : power : : 1.2V : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
|
||||||
segments[4] : W18 : output : 2.5 V : : 4A : Y
|
seg_a[4] : W18 : output : 1.2 V : : 4A : Y
|
||||||
GND : W19 : gnd : : : :
|
GND : W19 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W20 : : : : 5A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
|
||||||
@@ -738,10 +738,10 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : :
|
|||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 4A :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4A :
|
||||||
VCCIO4A : Y17 : power : : 2.5V : 4A :
|
VCCIO4A : Y17 : power : : 1.2V : 4A :
|
||||||
segments[7] : Y18 : output : 2.5 V : : 4A : Y
|
seg_a[7] : Y18 : output : 1.2 V : : 4A : Y
|
||||||
segments[6] : Y19 : output : 2.5 V : : 4A : Y
|
seg_a[6] : Y19 : output : 1.2 V : : 4A : Y
|
||||||
segments[5] : Y20 : output : 2.5 V : : 4A : Y
|
seg_a[5] : Y20 : output : 1.2 V : : 4A : Y
|
||||||
VCCA_FPLL : Y21 : power : : 2.5V : :
|
VCCA_FPLL : Y21 : power : : 2.5V : :
|
||||||
GND : Y22 : gnd : : : :
|
GND : Y22 : gnd : : : :
|
||||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
|
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5A :
|
||||||
|
|||||||
Binary file not shown.
@@ -1,5 +1,5 @@
|
|||||||
Timing Analyzer report for seven_seg
|
Timing Analyzer report for seven_seg
|
||||||
Tue Sep 15 16:10:29 2026
|
Tue Sep 15 21:07:17 2026
|
||||||
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
|
|
||||||
|
|
||||||
@@ -103,7 +103,7 @@ on the Quartus Prime software download page.
|
|||||||
; ; ;
|
; ; ;
|
||||||
; Usage by Processor ; % Time Used ;
|
; Usage by Processor ; % Time Used ;
|
||||||
; Processor 1 ; 100.0% ;
|
; Processor 1 ; 100.0% ;
|
||||||
; Processor 2 ; 2.0% ;
|
; Processor 2 ; 2.2% ;
|
||||||
+----------------------------+-------------+
|
+----------------------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -285,97 +285,140 @@ No synchronizer chains to report.
|
|||||||
+------------------+-------+------+----------+---------+---------------------+
|
+------------------+-------+------+----------+---------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Board Trace Model Assignments ;
|
; Board Trace Model Assignments ;
|
||||||
+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||||
+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||||
; segments[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[0] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
; segments[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
; seg_b[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
; seg_a[0] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[1] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[2] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[3] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[4] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[5] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[6] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
; seg_a[7] ; 1.2 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||||
|
+----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------+
|
||||||
; Input Transition Times ;
|
; Input Transition Times ;
|
||||||
+------------+--------------+-----------------+-----------------+
|
+------+--------------+-----------------+-----------------+
|
||||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||||
+------------+--------------+-----------------+-----------------+
|
+------+--------------+-----------------+-----------------+
|
||||||
; num[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
; b[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
; rbi_inv[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
; b[1] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
; num[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
; b[2] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
; num[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
; b[3] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
; num[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
; a[0] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
+------------+--------------+-----------------+-----------------+
|
; a[1] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
|
; a[2] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
|
; a[3] ; 1.2 V ; 960 ps ; 960 ps ;
|
||||||
|
+------+--------------+-----------------+-----------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
|
; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; segments[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ; 2.32 V ; 2.15e-07 V ; 2.41 V ; -0.0495 V ; 0.18 V ; 0.115 V ; 4.54e-10 s ; 4.44e-10 s ; No ; Yes ;
|
; seg_b[0] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
; seg_b[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||||
; segments[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
; seg_b[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
; seg_b[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
; seg_b[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
; seg_b[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0538 V ; 0.13 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ; 2.32 V ; 1.88e-07 V ; 2.35 V ; -0.0185 V ; 0.153 V ; 0.099 V ; 4.6e-10 s ; 4.48e-10 s ; No ; Yes ;
|
; seg_b[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
; segments[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ; 2.32 V ; 2.19e-07 V ; 2.4 V ; -0.039 V ; 0.21 V ; 0.145 V ; 4.67e-10 s ; 4.63e-10 s ; No ; Yes ;
|
; seg_b[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ; 1.09 V ; 1.24e-07 V ; 1.12 V ; -0.0517 V ; 0.131 V ; 0.103 V ; 4.91e-10 s ; 4.61e-10 s ; No ; No ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
; seg_a[0] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||||
|
; seg_a[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||||
|
; seg_a[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ; 1.09 V ; 1.12e-07 V ; 1.1 V ; -0.0175 V ; 0.055 V ; 0.073 V ; 6.35e-10 s ; 4.59e-10 s ; No ; No ;
|
||||||
|
; seg_a[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ; 1.09 V ; 1.26e-07 V ; 1.12 V ; -0.0464 V ; 0.081 V ; 0.112 V ; 6.59e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; segments[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ; 2.32 V ; 2.52e-05 V ; 2.38 V ; -0.0315 V ; 0.205 V ; 0.182 V ; 4.74e-10 s ; 4.85e-10 s ; No ; Yes ;
|
; seg_b[0] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||||
; segments[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
; seg_b[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||||
; segments[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
; seg_b[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||||
; segments[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
; seg_b[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||||
; segments[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
; seg_b[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||||
; segments[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
; seg_b[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0321 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.83e-10 s ; No ; No ;
|
||||||
; segments[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ; 2.32 V ; 2.27e-05 V ; 2.34 V ; -0.0089 V ; 0.206 V ; 0.058 V ; 4.97e-10 s ; 5.13e-10 s ; Yes ; Yes ;
|
; seg_b[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||||
; segments[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ; 2.32 V ; 2.56e-05 V ; 2.38 V ; -0.026 V ; 0.249 V ; 0.089 V ; 4.95e-10 s ; 6.01e-10 s ; No ; Yes ;
|
; seg_b[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ; 1.09 V ; 1.73e-05 V ; 1.11 V ; -0.0316 V ; 0.075 V ; 0.122 V ; 6.54e-10 s ; 4.82e-10 s ; No ; No ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
; seg_a[0] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||||
|
; seg_a[1] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||||
|
; seg_a[2] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||||
|
; seg_a[3] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||||
|
; seg_a[4] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||||
|
; seg_a[5] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||||
|
; seg_a[6] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ; 1.09 V ; 1.61e-05 V ; 1.09 V ; -0.0084 V ; 0.066 V ; 0.108 V ; 6.59e-10 s ; 5.03e-10 s ; Yes ; Yes ;
|
||||||
|
; seg_a[7] ; 1.2 V ; 0 s ; 0 s ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ; 1.09 V ; 1.76e-05 V ; 1.11 V ; -0.0281 V ; 0.09 V ; 0.14 V ; 6.73e-10 s ; 5.04e-10 s ; No ; No ;
|
||||||
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; segments[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
|
; seg_b[0] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
; seg_b[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
; segments[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
; seg_b[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
; seg_b[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
; seg_b[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
; seg_b[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0985 V ; 0.168 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
|
; seg_b[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
; segments[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
|
; seg_b[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ; 1.32 V ; 2e-06 V ; 1.42 V ; -0.0978 V ; 0.167 V ; 0.193 V ; 2.62e-10 s ; 2.77e-10 s ; No ; No ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
; seg_a[0] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 1.78e-06 V ; 1.36 V ; -0.0397 V ; 0.144 V ; 0.155 V ; 2.76e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
; seg_a[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ; 1.32 V ; 2.04e-06 V ; 1.41 V ; -0.082 V ; 0.189 V ; 0.214 V ; 2.71e-10 s ; 2.9e-10 s ; No ; No ;
|
||||||
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
; segments[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
|
; seg_b[0] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
; seg_b[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||||
; segments[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
; seg_b[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
; seg_b[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
; seg_b[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
; seg_b[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.056 V ; 0.186 V ; 0.116 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
|
; seg_b[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
; segments[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
|
; seg_b[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ; 1.32 V ; 0.000145 V ; 1.4 V ; -0.0574 V ; 0.186 V ; 0.115 V ; 2.8e-10 s ; 4.6e-10 s ; No ; No ;
|
||||||
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
; seg_a[0] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[1] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[2] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[3] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||||
|
; seg_a[4] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||||
|
; seg_a[5] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
; seg_a[6] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ; 1.32 V ; 0.000132 V ; 1.35 V ; -0.0188 V ; 0.072 V ; 0.082 V ; 4.35e-10 s ; 4.57e-10 s ; No ; No ;
|
||||||
|
; seg_a[7] ; 1.2 V ; 0 s ; 0 s ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ; 1.32 V ; 0.000148 V ; 1.39 V ; -0.0478 V ; 0.214 V ; 0.125 V ; 2.99e-10 s ; 4.71e-10 s ; No ; No ;
|
||||||
|
+----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||||
|
|
||||||
|
|
||||||
-------------------
|
-------------------
|
||||||
@@ -403,10 +446,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
; Illegal Clocks ; 0 ; 0 ;
|
; Illegal Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Clocks ; 0 ; 0 ;
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Input Ports ; 5 ; 5 ;
|
; Unconstrained Input Ports ; 8 ; 8 ;
|
||||||
; Unconstrained Input Port Paths ; 39 ; 39 ;
|
; Unconstrained Input Port Paths ; 60 ; 60 ;
|
||||||
; Unconstrained Output Ports ; 8 ; 8 ;
|
; Unconstrained Output Ports ; 15 ; 15 ;
|
||||||
; Unconstrained Output Port Paths ; 39 ; 39 ;
|
; Unconstrained Output Port Paths ; 60 ; 60 ;
|
||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
|
|
||||||
|
|
||||||
@@ -415,11 +458,14 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
; Input Port ; Comment ;
|
; Input Port ; Comment ;
|
||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
; num[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; rbi_inv[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; b[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -428,14 +474,21 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
; Output Port ; Comment ;
|
; Output Port ; Comment ;
|
||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
; segments[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_b[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -444,11 +497,14 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
; Input Port ; Comment ;
|
; Input Port ; Comment ;
|
||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
; num[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; num[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; a[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; rbi_inv[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; b[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; b[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
+------------+--------------------------------------------------------------------------------------+
|
+------------+--------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -457,14 +513,21 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
; Output Port ; Comment ;
|
; Output Port ; Comment ;
|
||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
; segments[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_a[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
; segments[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
; seg_b[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
|
; seg_b[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||||
+-------------+---------------------------------------------------------------------------------------+
|
+-------------+---------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
@@ -474,7 +537,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus Prime Timing Analyzer
|
Info: Running Quartus Prime Timing Analyzer
|
||||||
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
|
||||||
Info: Processing started: Tue Sep 15 16:10:24 2026
|
Info: Processing started: Tue Sep 15 21:07:11 2026
|
||||||
Info: Command: quartus_sta q1 -c seven_seg
|
Info: Command: quartus_sta q1 -c seven_seg
|
||||||
Info: qsta_default_script.tcl version: #1
|
Info: qsta_default_script.tcl version: #1
|
||||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||||
@@ -534,9 +597,9 @@ Info (332140): No Minimum Pulse Width paths to report
|
|||||||
Info (332102): Design is not fully constrained for setup requirements
|
Info (332102): Design is not fully constrained for setup requirements
|
||||||
Info (332102): Design is not fully constrained for hold requirements
|
Info (332102): Design is not fully constrained for hold requirements
|
||||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings
|
||||||
Info: Peak virtual memory: 788 megabytes
|
Info: Peak virtual memory: 769 megabytes
|
||||||
Info: Processing ended: Tue Sep 15 16:10:29 2026
|
Info: Processing ended: Tue Sep 15 21:07:17 2026
|
||||||
Info: Elapsed time: 00:00:05
|
Info: Elapsed time: 00:00:06
|
||||||
Info: Total CPU time (on all processors): 00:00:06
|
Info: Total CPU time (on all processors): 00:00:06
|
||||||
|
|
||||||
|
|
||||||
+52
-14
@@ -39,7 +39,7 @@
|
|||||||
|
|
||||||
set_global_assignment -name FAMILY "Cyclone V"
|
set_global_assignment -name FAMILY "Cyclone V"
|
||||||
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
|
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
|
||||||
set_global_assignment -name TOP_LEVEL_ENTITY seven_seg
|
set_global_assignment -name TOP_LEVEL_ENTITY seven_seg_2digit
|
||||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
|
||||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:41 SEPTEMBER 03, 2026"
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:41 SEPTEMBER 03, 2026"
|
||||||
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
|
set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
|
||||||
@@ -58,17 +58,55 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
|
|||||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||||
set_location_assignment PIN_F7 -to segments[0]
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||||
set_location_assignment PIN_V19 -to segments[1]
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||||
set_location_assignment PIN_V18 -to segments[2]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[0]
|
||||||
set_location_assignment PIN_V17 -to segments[3]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[1]
|
||||||
set_location_assignment PIN_W18 -to segments[4]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[2]
|
||||||
set_location_assignment PIN_Y20 -to segments[5]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[3]
|
||||||
set_location_assignment PIN_Y19 -to segments[6]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[4]
|
||||||
set_location_assignment PIN_Y18 -to segments[7]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[5]
|
||||||
set_location_assignment PIN_AC9 -to num[0]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[6]
|
||||||
set_location_assignment PIN_AE10 -to num[1]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b[7]
|
||||||
set_location_assignment PIN_AD13 -to num[2]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_b
|
||||||
set_location_assignment PIN_AC8 -to num[3]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[0]
|
||||||
set_location_assignment PIN_AE19 -to rbi_inv[0]
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[1]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[2]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[3]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[4]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[5]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[6]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a[7]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to seg_a
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to b[0]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to b[1]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to b[2]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to a[0]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to b[3]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to b
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to a[1]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to a[2]
|
||||||
|
set_instance_assignment -name IO_STANDARD "1.2 V" -to a[3]
|
||||||
|
set_location_assignment PIN_V19 -to seg_a[1]
|
||||||
|
set_location_assignment PIN_V18 -to seg_a[2]
|
||||||
|
set_location_assignment PIN_V17 -to seg_a[3]
|
||||||
|
set_location_assignment PIN_W18 -to seg_a[4]
|
||||||
|
set_location_assignment PIN_Y20 -to seg_a[5]
|
||||||
|
set_location_assignment PIN_Y19 -to seg_a[6]
|
||||||
|
set_location_assignment PIN_Y18 -to seg_a[7]
|
||||||
|
set_location_assignment PIN_AA18 -to seg_b[1]
|
||||||
|
set_location_assignment PIN_AD26 -to seg_b[2]
|
||||||
|
set_location_assignment PIN_AB19 -to seg_b[3]
|
||||||
|
set_location_assignment PIN_AE26 -to seg_b[4]
|
||||||
|
set_location_assignment PIN_AE25 -to seg_b[5]
|
||||||
|
set_location_assignment PIN_AC19 -to seg_b[6]
|
||||||
|
set_location_assignment PIN_AF24 -to seg_b[7]
|
||||||
|
set_location_assignment PIN_AC9 -to a[0]
|
||||||
|
set_location_assignment PIN_AE10 -to a[1]
|
||||||
|
set_location_assignment PIN_AD13 -to a[2]
|
||||||
|
set_location_assignment PIN_AC8 -to a[3]
|
||||||
|
set_location_assignment PIN_W11 -to b[0]
|
||||||
|
set_location_assignment PIN_AB10 -to b[1]
|
||||||
|
set_location_assignment PIN_V10 -to b[2]
|
||||||
|
set_location_assignment PIN_AC10 -to b[3]
|
||||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||||
Binary file not shown.
+51
-22
@@ -1,26 +1,55 @@
|
|||||||
`ifndef SEVEN_SEG_H_SV
|
`ifndef SEVEN_SEG_H_SV
|
||||||
`define SEVEN_SEG_H_SV
|
`define SEVEN_SEG_H_SV
|
||||||
module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
|
|
||||||
always_comb begin
|
module seven_seg(
|
||||||
case (num)
|
input logic [3:0] num,
|
||||||
4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
|
input logic [0:0] rbi_inv,
|
||||||
4'b0001: segments = ~(8'b00001101);
|
output logic [7:0] segments);
|
||||||
4'b0010: segments = ~(8'b10110111);
|
|
||||||
4'b0011: segments = ~(8'b10011111);
|
always_comb begin
|
||||||
4'b0100: segments = ~(8'b11001101);
|
case (num)
|
||||||
4'b0101: segments = ~(8'b11011011);
|
4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); // zero or blank
|
||||||
4'b0110: segments = ~(8'b11111011);
|
4'b0001: segments = ~(8'b00001101);
|
||||||
4'b0111: segments = ~(8'b00001111);
|
4'b0010: segments = ~(8'b10110111);
|
||||||
4'b1000: segments = ~(8'b11111111);
|
4'b0011: segments = ~(8'b10011111);
|
||||||
4'b1001: segments = ~(8'b11001111);
|
4'b0100: segments = ~(8'b11001101);
|
||||||
4'b1010: segments = ~(8'b11101111);
|
4'b0101: segments = ~(8'b11011011);
|
||||||
4'b1011: segments = ~(8'b11111001);
|
4'b0110: segments = ~(8'b11111011);
|
||||||
4'b1100: segments = ~(8'b01110011);
|
4'b0111: segments = ~(8'b00001111);
|
||||||
4'b1101: segments = ~(8'b10111101);
|
4'b1000: segments = ~(8'b11111111);
|
||||||
4'b1110: segments = ~(8'b11110011);
|
4'b1001: segments = ~(8'b11001111);
|
||||||
4'b1111: segments = ~(8'b11100011);
|
4'b1010: segments = ~(8'b11101111);
|
||||||
default: segments = ~(8'bxxxxxxxx);
|
4'b1011: segments = ~(8'b11111001);
|
||||||
endcase
|
4'b1100: segments = ~(8'b01110011);
|
||||||
end
|
4'b1101: segments = ~(8'b10111101);
|
||||||
|
4'b1110: segments = ~(8'b11110011);
|
||||||
|
4'b1111: segments = ~(8'b11100011);
|
||||||
|
default: segments = ~(8'bxxxxxxxx);
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module seven_seg_2digit(
|
||||||
|
input logic [3:0] b, // left
|
||||||
|
input logic [3:0] a, // right
|
||||||
|
output logic [7:0] seg_b, // left
|
||||||
|
output logic [7:0] seg_a); // right
|
||||||
|
|
||||||
|
logic rbo_b;
|
||||||
|
|
||||||
|
// seg_b
|
||||||
|
seven_seg left_digit(
|
||||||
|
.num(b),
|
||||||
|
.rbi_inv(1'b0), // blanking enabled
|
||||||
|
.segments(seg_b)
|
||||||
|
);
|
||||||
|
|
||||||
|
// seg_a
|
||||||
|
seven_seg right_digit(
|
||||||
|
.num(a),
|
||||||
|
.rbi_inv(1'b1), // blanking disabled
|
||||||
|
.segments(seg_a)
|
||||||
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
`endif
|
`endif
|
||||||
@@ -0,0 +1,26 @@
|
|||||||
|
`ifndef SEVEN_SEG_H_SV
|
||||||
|
`define SEVEN_SEG_H_SV
|
||||||
|
module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments);
|
||||||
|
always_comb begin
|
||||||
|
case (num)
|
||||||
|
4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000);
|
||||||
|
4'b0001: segments = ~(8'b00001101);
|
||||||
|
4'b0010: segments = ~(8'b10110111);
|
||||||
|
4'b0011: segments = ~(8'b10011111);
|
||||||
|
4'b0100: segments = ~(8'b11001101);
|
||||||
|
4'b0101: segments = ~(8'b11011011);
|
||||||
|
4'b0110: segments = ~(8'b11111011);
|
||||||
|
4'b0111: segments = ~(8'b00001111);
|
||||||
|
4'b1000: segments = ~(8'b11111111);
|
||||||
|
4'b1001: segments = ~(8'b11001111);
|
||||||
|
4'b1010: segments = ~(8'b11101111);
|
||||||
|
4'b1011: segments = ~(8'b11111001);
|
||||||
|
4'b1100: segments = ~(8'b01110011);
|
||||||
|
4'b1101: segments = ~(8'b10111101);
|
||||||
|
4'b1110: segments = ~(8'b11110011);
|
||||||
|
4'b1111: segments = ~(8'b11100011);
|
||||||
|
default: segments = ~(8'bxxxxxxxx);
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
File renamed without changes.
File diff suppressed because it is too large.
Load diff
Binary file not shown.
Reference in new issue
Block a user