Implemented ALU. Still needs testbench and testing done.

modules/alu.sv

@@ -9,12 +9,24 @@ module alu #(parameter width=2)(input logic [3:0] op,
 
     logic [2**width-1:0] asu_out;
     logic [1:0] asu_flags;
-    logic [0:0] asu_op;
+    asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
-    asu #(width) adder_unit(asu_op, A, B, asu_out, asu_flags[0], asu_flags[1]);
 
     logic [width-1:0] lu_out;
     lu #(width) logic_unit(op[1:0], A, B, lu_out);
 
-    // Cout = asu_flags[0]
+    always_comb begin
-    // Overflow = asu_flags[0] ^ asu_flags[1]
+        case (op) 
+            2'b0000: begin OUT_1 = asu_out; flags = asu_flags; end
+            2'b0001: begin OUT_1 = asu_out; flags = asu_flags; end
+            2'b0010: begin OUT_1 = asu_out; flags = asu_flags; end
+            2'b0011: begin OUT_1 = asu_out; flags = asu_flags; end
+            2'b0100: OUT_1 = lu_out;
+            2'b0101: OUT_1 = lu_out;
+            2'b0110: OUT_1 = lu_out; 
+            2'b0111: OUT_1 = lu_out;
+            2'b1010: OUT_1 = (asu_out[$clog2(width)-1] ^ asu_flags[1]);
+            2'b1011: OUT_1 = ~asu_flags[0];
+            default: '0;
+        endcase
+    end
 endmodule