Temp change to make RAM word-aligned

modules/ram.sv

@@ -9,7 +9,8 @@ module ram #(addrwidth=9, datawidth=5)(
     output logic [datawidth-1:0] data_out
 );
 
-    logic [7:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
+    // TODO: Make this byte-sized, NOT word-sized!
+    logic [2**width-1:0] mem[(2**(addrwidth+$clog2(datawidth)-3))-1:0];
 
     // NOTE: Possible issue with assignments still pending by end of initial block
     initial begin