Added comments to Logic Unit (Q2) and added to submission file
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@@ -1 +1,80 @@
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`ifndef LU_H_SV
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`define LU_H_SV
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module lu #(parameter width = 2) (
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input logic [1:0] op, // 2 bit operand
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input logic [2**width-1:0] A, // width defined as 2^n
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input logic [2**width-1:0] B,
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output logic [2**width-1:0] Y);
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always_comb begin
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case (op) // different operations of A and B based on operand
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2'b00: Y = A & B;
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2'b01: Y = A | B;
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2'b10: Y = A ^ B;
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2'b11: Y = ~(A | B);
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default:Y = '0;
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endcase
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end
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endmodule
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`endif
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// Testbench
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module lu_tb #(parameter W=4)();
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logic [1:0] op;
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logic [W-1:0] A;
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logic [W-1:0] B;
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logic [W-1:0] C;
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logic [W-1:0] C_exp[16]; // expected values
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lu #(W/2) dut(op, A, B, C); // width / 2 as was adapted from width-1 being standard
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integer error_count;
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initial begin // only need to check 1 bit for expected functionality
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// AND
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C_exp[0] = {{W{1'b0}}, {1'b0}};
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C_exp[1] = {{W{1'b0}}, {1'b0}};
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C_exp[2] = {{W{1'b0}}, {1'b0}};
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C_exp[3] = {{W{1'b0}}, {1'b1}};
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// OR
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C_exp[4] = {{W{1'b0}}, {1'b0}};
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C_exp[5] = {{W{1'b0}}, {1'b1}};
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C_exp[6] = {{W{1'b0}}, {1'b1}};
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C_exp[7] = {{W{1'b0}}, {1'b1}};
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// XOR
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C_exp[8] = {{W{1'b0}}, {1'b0}};
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C_exp[9] = {{W{1'b0}}, {1'b1}};
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C_exp[10] = {{W{1'b0}}, {1'b1}};
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C_exp[11] = {{W{1'b0}}, {1'b0}};
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// NOR
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C_exp[12] = {{W{1'b1}}, {1'b1}};
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C_exp[13] = {{W{1'b1}}, {1'b0}};
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C_exp[14] = {{W{1'b1}}, {1'b0}};
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C_exp[15] = {{W{1'b1}}, {1'b0}};
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error_count = 0;
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op = 0;
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A = 0;
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B = 0;
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$display("Beginning LU tests"); // find difference between calculated and excpected
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for (integer N = 0; N < 4; ++N) begin
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for (integer M = 0; M < 2; ++M) begin
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for (integer K = 0; K < 2; ++K) begin
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#1;
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if (C != C_exp[N*2*2 + M*2 + K]) begin
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$display("\t\x1b[38;5;9mLU(%0d) Op 0b%b(0b%b, 0b%b) produced 0b%b but 0b%b was expected\x1b[m", N*2*2+M*2+K, op, A, B, C, C_exp[N*2*2 + M*2 + K]);
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error_count = error_count + 1;
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end
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B = 1;
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end
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A = 1;
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B = 0;
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end
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A = 0;
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B = 0;
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op = op + 1;
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end
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if (error_count == 0) $display("\x1b[38;5;10mAll LU tests passing\x1b[m");
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else $display("\x1b[38;5;9m%0d LU test(s) failing\x1b[m", error_count);
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end
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endmodule
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