TroubleElectrical/FPGA_Uni
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Fixed bug of confuddling width with 2^n and w.

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riley committed 2026-09-10 15:42:50 +10:00
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commit 37644c629e
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modules/alu.sv
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@@ -11,7 +11,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
logic [1:0] asu_flags; logic [1:0] asu_flags;
asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]); asu #(width) adder_unit(asu_op[op[1]], A, B, asu_out, asu_flags[0], asu_flags[1]);
logic [width-1:0] lu_out; logic [2**width-1:0] lu_out;
lu #(width) logic_unit(op[1:0], A, B, lu_out); lu #(width) logic_unit(op[1:0], A, B, lu_out);
always_comb begin always_comb begin
@@ -24,7 +24,7 @@ module alu #(parameter width=2)(input logic [3:0] op,
2'b0101: OUT_1 = lu_out; 2'b0101: OUT_1 = lu_out;
2'b0110: OUT_1 = lu_out; 2'b0110: OUT_1 = lu_out;
2'b0111: OUT_1 = lu_out; 2'b0111: OUT_1 = lu_out;
2'b1010: OUT_1 = (asu_out[$clog2(width)-1] ^ asu_flags[1]); 2'b1010: OUT_1 = (asu_out[2**width-1] ^ asu_flags[1]);
2'b1011: OUT_1 = ~asu_flags[0]; 2'b1011: OUT_1 = ~asu_flags[0];
default: '0; default: '0;
endcase endcase