From 32eea036a8bfd47f599a2e467a83a576fa1e6457 Mon Sep 17 00:00:00 2001 From: TroubleElectrical Date: Fri, 4 Sep 2026 13:12:33 +1000 Subject: [PATCH] Added projects for A1 q2 to q6 --- Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock | 0 Quartus/A1_Q1/db/seven_seg.tmw_info | 11 ++-- Quartus/A1_Q1/seven_seg.qws | Bin 0 -> 654 bytes Quartus/A1_Q2/A1_Q2.qpf | 31 ++++++++++ Quartus/A1_Q2/db/lu.db_info | 3 + Quartus/A1_Q2/db/lu.pplq.rdb | Bin 0 -> 304 bytes Quartus/A1_Q2/db/lu.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A1_Q2/lu.qsf | 57 ++++++++++++++++++ Quartus/A1_Q2/lu.qws | Bin 0 -> 682 bytes Quartus/A1_Q3/A1_Q3.qpf | 31 ++++++++++ Quartus/A1_Q3/asu.qsf | 57 ++++++++++++++++++ Quartus/A1_Q3/asu.qws | Bin 0 -> 686 bytes Quartus/A1_Q3/db/asu.db_info | 3 + Quartus/A1_Q3/db/asu.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A1_Q4/A1_Q4.qpf | 31 ++++++++++ Quartus/A1_Q4/alu.qsf | 57 ++++++++++++++++++ Quartus/A1_Q4/alu.qws | Bin 0 -> 686 bytes Quartus/A1_Q4/db/alu.db_info | 3 + Quartus/A1_Q4/db/alu.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A1_Q5/A1_Q5.qpf | 31 ++++++++++ Quartus/A1_Q5/db/shifter.db_info | 3 + Quartus/A1_Q5/db/shifter.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A1_Q5/shifter.qsf | 57 ++++++++++++++++++ Quartus/A1_Q5/shifter.qws | Bin 0 -> 702 bytes Quartus/A1_Q6/A1_Q6.qpf | 31 ++++++++++ .../A1_Q6/db/instruction_classifier.db_info | 3 + ...nstruction_classifier.sld_design_entry.sci | Bin 0 -> 229 bytes Quartus/A1_Q6/instruction_classifier.qsf | 57 ++++++++++++++++++ Quartus/A1_Q6/instruction_classifier.qws | Bin 0 -> 762 bytes 29 files changed, 459 insertions(+), 7 deletions(-) delete mode 100644 Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock create mode 100644 Quartus/A1_Q1/seven_seg.qws create mode 100644 Quartus/A1_Q2/A1_Q2.qpf create mode 100644 Quartus/A1_Q2/db/lu.db_info create mode 100644 Quartus/A1_Q2/db/lu.pplq.rdb create mode 100644 Quartus/A1_Q2/db/lu.sld_design_entry.sci create mode 100644 Quartus/A1_Q2/lu.qsf create mode 100644 Quartus/A1_Q2/lu.qws create mode 100644 Quartus/A1_Q3/A1_Q3.qpf create mode 100644 Quartus/A1_Q3/asu.qsf create mode 100644 Quartus/A1_Q3/asu.qws create mode 100644 Quartus/A1_Q3/db/asu.db_info create mode 100644 Quartus/A1_Q3/db/asu.sld_design_entry.sci create mode 100644 Quartus/A1_Q4/A1_Q4.qpf create mode 100644 Quartus/A1_Q4/alu.qsf create mode 100644 Quartus/A1_Q4/alu.qws create mode 100644 Quartus/A1_Q4/db/alu.db_info create mode 100644 Quartus/A1_Q4/db/alu.sld_design_entry.sci create mode 100644 Quartus/A1_Q5/A1_Q5.qpf create mode 100644 Quartus/A1_Q5/db/shifter.db_info create mode 100644 Quartus/A1_Q5/db/shifter.sld_design_entry.sci create mode 100644 Quartus/A1_Q5/shifter.qsf create mode 100644 Quartus/A1_Q5/shifter.qws create mode 100644 Quartus/A1_Q6/A1_Q6.qpf create mode 100644 Quartus/A1_Q6/db/instruction_classifier.db_info create mode 100644 Quartus/A1_Q6/db/instruction_classifier.sld_design_entry.sci create mode 100644 Quartus/A1_Q6/instruction_classifier.qsf create mode 100644 Quartus/A1_Q6/instruction_classifier.qws diff --git a/Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock b/Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock deleted file mode 100644 index e69de29..0000000 diff --git a/Quartus/A1_Q1/db/seven_seg.tmw_info b/Quartus/A1_Q1/db/seven_seg.tmw_info index a784bf2..1bd50f7 100644 --- a/Quartus/A1_Q1/db/seven_seg.tmw_info +++ b/Quartus/A1_Q1/db/seven_seg.tmw_info @@ -1,7 +1,4 @@ -start_full_compilation:s:00:00:58 -start_analysis_synthesis:s:00:00:13-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:29-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation -start_eda_netlist_writer:s:00:00:03-start_full_compilation +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation +start_eda_netlist_writer:s-start_full_compilation diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws new file mode 100644 index 0000000000000000000000000000000000000000..0ccf1da245c3cc658b932a03b9dd28c94ca4589d GIT binary patch literal 654 zcmbV}F-rqM5QX1)3Mo^Gg+&UHAe=;vG3g|rRVuL$dTumCbK$%sg7^n)^Rv>}+WRw< z_|0->5hS2Oe26-ZL@5E6W1t%N8jd zlLT7NQNou#^8lwcu&WNLdh}UQTVs4iw?m>!e8Lp2QIHx{3(S0OWt~&%kZzP%gWpJA z8U6`?6Kv)Fpu_$W^Jb)NYRC#h=g literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q2/A1_Q2.qpf b/Quartus/A1_Q2/A1_Q2.qpf new file mode 100644 index 0000000..c1a2061 --- /dev/null +++ b/Quartus/A1_Q2/A1_Q2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:57:20 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "12:57:20 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "lu" diff --git a/Quartus/A1_Q2/db/lu.db_info b/Quartus/A1_Q2/db/lu.db_info new file mode 100644 index 0000000..25dba9a --- /dev/null +++ b/Quartus/A1_Q2/db/lu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 12:57:24 2026 diff --git a/Quartus/A1_Q2/db/lu.pplq.rdb b/Quartus/A1_Q2/db/lu.pplq.rdb new file mode 100644 index 0000000000000000000000000000000000000000..e1f255ec442d345b222da9d2f7366eea1c0e76b4 GIT binary patch literal 304 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KccY_UKU^ot?`=B(4GJx2?P{Ej#n2_**F-amJCFKG8 zCT640B1}a>pFah4i`;RxP2BXtL^;5cxtT#=Go#^z!<>WCjv74|9`N#DFO)z2^qgK7N6!=GP7ZZbVqZ{oJY+u%zv7l zW=JSC{P}Z9{*^;lqhv?or+&_{j;gNLM=zjj5dE=Mn4FUqqUv~fey<-R4QRgWe a8>SYrEj@N{O5++8jz%peutfmYbZM{v literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q2/db/lu.sld_design_entry.sci b/Quartus/A1_Q2/db/lu.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..7a5b911bc97025e01fac4c7ee13ae5fa692fcce6 GIT binary patch literal 229 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q2/lu.qsf b/Quartus/A1_Q2/lu.qsf new file mode 100644 index 0000000..ff07833 --- /dev/null +++ b/Quartus/A1_Q2/lu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:57:20 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# lu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY lu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:57:20 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/lu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q2/lu.qws b/Quartus/A1_Q2/lu.qws new file mode 100644 index 0000000000000000000000000000000000000000..cefa2eb9bb49ef322a83e867a150b4504c23e6a9 GIT binary patch literal 682 zcmbV}F-rqM5QX1)3Ms9uEG#4h;Y`%1v6FySsl;CN+-QjL!sSi{@ekPgvuteb{TWL9 zX4$g{BI+z}=4SWJ?3=y)hALaul}KMc* zsfOQ?yfg|LI?_NFy8O>g*4VJ>MU8)!>ebCiU82zG&fk52;DMhqH*vF5#cbLB8qbkI lv*#H7{l;$e`tmGm_GNKF=cg()g=Uu9YzuGI3BS%WKLHIzZOQ-u literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q3/A1_Q3.qpf b/Quartus/A1_Q3/A1_Q3.qpf new file mode 100644 index 0000000..9a07fd3 --- /dev/null +++ b/Quartus/A1_Q3/A1_Q3.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:02:41 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:02:41 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "asu" diff --git a/Quartus/A1_Q3/asu.qsf b/Quartus/A1_Q3/asu.qsf new file mode 100644 index 0000000..8550cd7 --- /dev/null +++ b/Quartus/A1_Q3/asu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:02:41 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# asu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY asu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:02:41 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/asu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q3/asu.qws b/Quartus/A1_Q3/asu.qws new file mode 100644 index 0000000000000000000000000000000000000000..47d9a931b41d558a05ba8d521b13d327e2c4d322 GIT binary patch literal 686 zcmbV}F-rqM5QX1)3Mo@rSy+f1!X;6o#!dpJN+tH9=SD+}7cO@yh=0J=pJiif@6S-; zH_M$x5FyU;c5Zgx%)Hqj z&n~!|>aOJX^+@(EH#_VO?-ctuQH!s(_S6Bf4yk0kSo<2VS~?&yv_VJPdRnBvi4C6F zWd8_7!}A<~J4y3+N3I$2@Eh8H#YTdG$#Cv}xXrw8Br7{Nn7WoF{$rwTc;^DUku lg=Wt&Uc6&Bcz=7975lL;r}9e`nnE*+ZMKz<>V{wEncp85Zk_-D literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q3/db/asu.db_info b/Quartus/A1_Q3/db/asu.db_info new file mode 100644 index 0000000..dff2732 --- /dev/null +++ b/Quartus/A1_Q3/db/asu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:02:46 2026 diff --git a/Quartus/A1_Q3/db/asu.sld_design_entry.sci b/Quartus/A1_Q3/db/asu.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..7a5b911bc97025e01fac4c7ee13ae5fa692fcce6 GIT binary patch literal 229 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q4/A1_Q4.qpf b/Quartus/A1_Q4/A1_Q4.qpf new file mode 100644 index 0000000..f756ba7 --- /dev/null +++ b/Quartus/A1_Q4/A1_Q4.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:06:02 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:06:02 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "alu" diff --git a/Quartus/A1_Q4/alu.qsf b/Quartus/A1_Q4/alu.qsf new file mode 100644 index 0000000..47c8adf --- /dev/null +++ b/Quartus/A1_Q4/alu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:06:02 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# alu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY alu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:06:02 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/alu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q4/alu.qws b/Quartus/A1_Q4/alu.qws new file mode 100644 index 0000000000000000000000000000000000000000..a22a1c57e2808553030ddeda3520224ccf6ae1df GIT binary patch literal 686 zcmbV}F-rqM5QX1)3Ms9uEG$G0;gYCPV;8LvQuKtj29>>jH)SSG1#(>DRqou zluU!)NM0HRiB8nlm9GDDlQlN1dr{-RrFwNUQdcN+dhmB2A-M0SEKJ<&R54q&zsYmt l(Cj%z^WWHs-rrtj&3-H{>HJcqrqIlCn{DZ%I^oxO<~IRlZjb-~ literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q4/db/alu.db_info b/Quartus/A1_Q4/db/alu.db_info new file mode 100644 index 0000000..7bb3efc --- /dev/null +++ b/Quartus/A1_Q4/db/alu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:06:05 2026 diff --git a/Quartus/A1_Q4/db/alu.sld_design_entry.sci b/Quartus/A1_Q4/db/alu.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..7a5b911bc97025e01fac4c7ee13ae5fa692fcce6 GIT binary patch literal 229 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q5/A1_Q5.qpf b/Quartus/A1_Q5/A1_Q5.qpf new file mode 100644 index 0000000..99982d9 --- /dev/null +++ b/Quartus/A1_Q5/A1_Q5.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:08:07 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:08:07 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "shifter" diff --git a/Quartus/A1_Q5/db/shifter.db_info b/Quartus/A1_Q5/db/shifter.db_info new file mode 100644 index 0000000..79de92a --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:08:10 2026 diff --git a/Quartus/A1_Q5/db/shifter.sld_design_entry.sci b/Quartus/A1_Q5/db/shifter.sld_design_entry.sci new file mode 100644 index 0000000000000000000000000000000000000000..7a5b911bc97025e01fac4c7ee13ae5fa692fcce6 GIT binary patch literal 229 zcmWe(U|?9w%?KnJ81jM80!W9Y78Pga=P4MO>KPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q5/shifter.qsf b/Quartus/A1_Q5/shifter.qsf new file mode 100644 index 0000000..789b93e --- /dev/null +++ b/Quartus/A1_Q5/shifter.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:08:07 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# shifter_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY shifter +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:07 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/shifter.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q5/shifter.qws b/Quartus/A1_Q5/shifter.qws new file mode 100644 index 0000000000000000000000000000000000000000..a133cfb5c0869889fb055230a88fb9f8b35de0c9 GIT binary patch literal 702 zcmbV}KT88a5XIkl3Ms9uEG#4h;S&Eu6FUiLl}hYI&y9u{FPs+@Bwrw{AIrwp-jAWg z-z<9;K?F0$+hKO!ynVBGR8tx2y48j5Rp?xg%9LwBHDWK7gA{>n)%hA>9m2ZOm_7%y z0dCY+4+Teeo%$j4b@hzO9$LGsj_j29Iz=;4Q~PRzM29FEFVO)?Jx*Ixh9+ohN0UW- znE7bRG6VXuMT*C40xbtr$d%7fkhBD<>f+X>+E9mS3%*QuRA=Oj=`V4X8&xyHa)?!( z(CQe;D5(a&k-Rk;YC7fhu6e@+ZZcuRrZ+YE+p2drXLXH6rzd~+F^2no%G}J&PZhIe q`&&Fm2F;#h`2QO_(fix0OzbD(0_B&oG=~;e+iWWzKPW7r05waIF)ARq$n5~8d)kB8t5At z>KhptnJNT3EBIuVq$;?kWR?KcyMYa1U}%QY#ZVeVJ%zF>7?TneSU)g`{�q_zM#J z{~supmXH#0@W6qDTYEx#1wD)z4b27Et*eji-oaMA>$jm{0mDxNhM>dDM~L4}%0PI^v A!~g&Q literal 0 HcmV?d00001 diff --git a/Quartus/A1_Q6/instruction_classifier.qsf b/Quartus/A1_Q6/instruction_classifier.qsf new file mode 100644 index 0000000..54d3982 --- /dev/null +++ b/Quartus/A1_Q6/instruction_classifier.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:11:22 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# instruction_classifier_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY instruction_classifier +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:11:22 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/instruction_classifier.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q6/instruction_classifier.qws b/Quartus/A1_Q6/instruction_classifier.qws new file mode 100644 index 0000000000000000000000000000000000000000..af28712478beafc7f7277c6e32e81494058b0830 GIT binary patch literal 762 zcmb`Ey-EX75QWdW3Ms9uEK-OBVH1C%#!doS1q-nkUGM4=lMS1V3gQdc`dBu$_CAIZ zzq#yM1Q8VPa_(g2o|!o_*>9*i%evN?#wv8GTV=}C#~Trg-=hKTOAN-kAB9B zv_qwY*IhhA8+5dxhyPb;g9ndXQ=kvKq;NtIXud=ZTYE1ZjOM_qdd!lri@LgOrQoxj z)OCW**vmP(bE9g?FoYYOd{Z?i4DRWJN? Gp7{wcfPUlv literal 0 HcmV?d00001