diff --git a/Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock b/Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock deleted file mode 100644 index e69de29..0000000 diff --git a/Quartus/A1_Q1/db/seven_seg.tmw_info b/Quartus/A1_Q1/db/seven_seg.tmw_info index a784bf2..1bd50f7 100644 --- a/Quartus/A1_Q1/db/seven_seg.tmw_info +++ b/Quartus/A1_Q1/db/seven_seg.tmw_info @@ -1,7 +1,4 @@ -start_full_compilation:s:00:00:58 -start_analysis_synthesis:s:00:00:13-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:29-start_full_compilation -start_assembler:s:00:00:07-start_full_compilation -start_timing_analyzer:s:00:00:06-start_full_compilation -start_eda_netlist_writer:s:00:00:03-start_full_compilation +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation +start_eda_netlist_writer:s-start_full_compilation diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws new file mode 100644 index 0000000..0ccf1da Binary files /dev/null and b/Quartus/A1_Q1/seven_seg.qws differ diff --git a/Quartus/A1_Q2/A1_Q2.qpf b/Quartus/A1_Q2/A1_Q2.qpf new file mode 100644 index 0000000..c1a2061 --- /dev/null +++ b/Quartus/A1_Q2/A1_Q2.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:57:20 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "12:57:20 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "lu" diff --git a/Quartus/A1_Q2/db/lu.db_info b/Quartus/A1_Q2/db/lu.db_info new file mode 100644 index 0000000..25dba9a --- /dev/null +++ b/Quartus/A1_Q2/db/lu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 12:57:24 2026 diff --git a/Quartus/A1_Q2/db/lu.pplq.rdb b/Quartus/A1_Q2/db/lu.pplq.rdb new file mode 100644 index 0000000..e1f255e Binary files /dev/null and b/Quartus/A1_Q2/db/lu.pplq.rdb differ diff --git a/Quartus/A1_Q2/db/lu.sld_design_entry.sci b/Quartus/A1_Q2/db/lu.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q2/db/lu.sld_design_entry.sci differ diff --git a/Quartus/A1_Q2/lu.qsf b/Quartus/A1_Q2/lu.qsf new file mode 100644 index 0000000..ff07833 --- /dev/null +++ b/Quartus/A1_Q2/lu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 12:57:20 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# lu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY lu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:57:20 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/lu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q2/lu.qws b/Quartus/A1_Q2/lu.qws new file mode 100644 index 0000000..cefa2eb Binary files /dev/null and b/Quartus/A1_Q2/lu.qws differ diff --git a/Quartus/A1_Q3/A1_Q3.qpf b/Quartus/A1_Q3/A1_Q3.qpf new file mode 100644 index 0000000..9a07fd3 --- /dev/null +++ b/Quartus/A1_Q3/A1_Q3.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:02:41 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:02:41 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "asu" diff --git a/Quartus/A1_Q3/asu.qsf b/Quartus/A1_Q3/asu.qsf new file mode 100644 index 0000000..8550cd7 --- /dev/null +++ b/Quartus/A1_Q3/asu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:02:41 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# asu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY asu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:02:41 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/asu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q3/asu.qws b/Quartus/A1_Q3/asu.qws new file mode 100644 index 0000000..47d9a93 Binary files /dev/null and b/Quartus/A1_Q3/asu.qws differ diff --git a/Quartus/A1_Q3/db/asu.db_info b/Quartus/A1_Q3/db/asu.db_info new file mode 100644 index 0000000..dff2732 --- /dev/null +++ b/Quartus/A1_Q3/db/asu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:02:46 2026 diff --git a/Quartus/A1_Q3/db/asu.sld_design_entry.sci b/Quartus/A1_Q3/db/asu.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q3/db/asu.sld_design_entry.sci differ diff --git a/Quartus/A1_Q4/A1_Q4.qpf b/Quartus/A1_Q4/A1_Q4.qpf new file mode 100644 index 0000000..f756ba7 --- /dev/null +++ b/Quartus/A1_Q4/A1_Q4.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:06:02 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:06:02 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "alu" diff --git a/Quartus/A1_Q4/alu.qsf b/Quartus/A1_Q4/alu.qsf new file mode 100644 index 0000000..47c8adf --- /dev/null +++ b/Quartus/A1_Q4/alu.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:06:02 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# alu_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY alu +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:06:02 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/alu.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q4/alu.qws b/Quartus/A1_Q4/alu.qws new file mode 100644 index 0000000..a22a1c5 Binary files /dev/null and b/Quartus/A1_Q4/alu.qws differ diff --git a/Quartus/A1_Q4/db/alu.db_info b/Quartus/A1_Q4/db/alu.db_info new file mode 100644 index 0000000..7bb3efc --- /dev/null +++ b/Quartus/A1_Q4/db/alu.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:06:05 2026 diff --git a/Quartus/A1_Q4/db/alu.sld_design_entry.sci b/Quartus/A1_Q4/db/alu.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q4/db/alu.sld_design_entry.sci differ diff --git a/Quartus/A1_Q5/A1_Q5.qpf b/Quartus/A1_Q5/A1_Q5.qpf new file mode 100644 index 0000000..99982d9 --- /dev/null +++ b/Quartus/A1_Q5/A1_Q5.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:08:07 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:08:07 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "shifter" diff --git a/Quartus/A1_Q5/db/shifter.db_info b/Quartus/A1_Q5/db/shifter.db_info new file mode 100644 index 0000000..79de92a --- /dev/null +++ b/Quartus/A1_Q5/db/shifter.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:08:10 2026 diff --git a/Quartus/A1_Q5/db/shifter.sld_design_entry.sci b/Quartus/A1_Q5/db/shifter.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q5/db/shifter.sld_design_entry.sci differ diff --git a/Quartus/A1_Q5/shifter.qsf b/Quartus/A1_Q5/shifter.qsf new file mode 100644 index 0000000..789b93e --- /dev/null +++ b/Quartus/A1_Q5/shifter.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:08:07 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# shifter_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY shifter +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:08:07 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/shifter.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q5/shifter.qws b/Quartus/A1_Q5/shifter.qws new file mode 100644 index 0000000..a133cfb Binary files /dev/null and b/Quartus/A1_Q5/shifter.qws differ diff --git a/Quartus/A1_Q6/A1_Q6.qpf b/Quartus/A1_Q6/A1_Q6.qpf new file mode 100644 index 0000000..24d0e21 --- /dev/null +++ b/Quartus/A1_Q6/A1_Q6.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:11:22 September 04, 2026 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "25.1" +DATE = "13:11:22 September 04, 2026" + +# Revisions + +PROJECT_REVISION = "instruction_classifier" diff --git a/Quartus/A1_Q6/db/instruction_classifier.db_info b/Quartus/A1_Q6/db/instruction_classifier.db_info new file mode 100644 index 0000000..fb20779 --- /dev/null +++ b/Quartus/A1_Q6/db/instruction_classifier.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +Version_Index = 604268800 +Creation_Time = Fri Sep 4 13:11:24 2026 diff --git a/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry.sci b/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry.sci new file mode 100644 index 0000000..7a5b911 Binary files /dev/null and b/Quartus/A1_Q6/db/instruction_classifier.sld_design_entry.sci differ diff --git a/Quartus/A1_Q6/instruction_classifier.qsf b/Quartus/A1_Q6/instruction_classifier.qsf new file mode 100644 index 0000000..54d3982 --- /dev/null +++ b/Quartus/A1_Q6/instruction_classifier.qsf @@ -0,0 +1,57 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2025 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus Prime License Agreement, +# the Altera IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Altera and sold by Altera or its authorized distributors. Please +# refer to the Altera Software License Subscription Agreements +# on the Quartus Prime software download page. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition +# Date created = 13:11:22 September 04, 2026 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# instruction_classifier_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY instruction_classifier +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:11:22 SEPTEMBER 04, 2026" +set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition" +set_global_assignment -name SYSTEMVERILOG_FILE ../../modules/instruction_classifier.sv +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Altera FPGA (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/A1_Q6/instruction_classifier.qws b/Quartus/A1_Q6/instruction_classifier.qws new file mode 100644 index 0000000..af28712 Binary files /dev/null and b/Quartus/A1_Q6/instruction_classifier.qws differ