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Including quartus prime lite edition project folders for flashing the project to the board

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TroubleElectrical committed 2026-09-03 16:34:31 +10:00
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Quartus/A1_Q1/output_files/seven_seg.eda.rpt
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EDA Netlist Writer report for seven_seg
Thu Sep 3 16:29:00 2026
Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2025 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Altera and sold by Altera or its authorized distributors. Please
refer to the Altera Software License Subscription Agreements
on the Quartus Prime software download page.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Sep 3 16:29:00 2026 ;
; Revision Name ; seven_seg ;
; Top-level Entity Name ; seven_seg ;
; Family ; Cyclone V ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
; Tool Name ; Questa Altera FPGA (SystemVerilog) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+----------------------------------------------------------------------------------------+
; Generated Files ;
+----------------------------------------------------------------------------------------+
; /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/seven_seg.svo ;
+----------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Info: Processing started: Thu Sep 3 16:28:59 2026
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 658 megabytes
Info: Processing ended: Thu Sep 3 16:29:00 2026
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01