diff --git a/Quartus/A1_Q1/db/prev_cmp_q1.qmsg b/Quartus/A1_Q1/db/prev_cmp_q1.qmsg index ca48cb7..9a5d9ba 100644 --- a/Quartus/A1_Q1/db/prev_cmp_q1.qmsg +++ b/Quartus/A1_Q1/db/prev_cmp_q1.qmsg @@ -1,135 +1,135 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788416577158 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416577158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:22:57 2026 " "Processing started: Thu Sep 3 16:22:57 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416577158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416577158 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416577158 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788416577474 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788416577474 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788416585806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416585806 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788416585939 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788416586671 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788416587031 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788416587031 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788416587059 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788416587059 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788416587059 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788416587059 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416587065 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:23:07 2026 " "Processing ended: Thu Sep 3 16:23:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416587065 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416587065 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416587065 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416587065 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788416588555 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416588556 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:23:08 2026 " "Processing started: Thu Sep 3 16:23:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416588556 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788416588556 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788416588556 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788416588617 ""} -{ "Info" "0" "" "Project = q1" { } { } 0 0 "Project = q1" 0 0 "Fitter" 0 0 1788416588618 ""} -{ "Info" "0" "" "Revision = seven_seg" { } { } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1788416588618 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788416588807 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788416588808 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788416588813 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788416588884 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788416588884 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788416589298 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788416589325 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788416589374 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788416596242 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416596260 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788416596262 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788416596263 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788416596264 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788416596264 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416596283 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788416602097 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788416602098 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788416602098 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788416602098 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788416602099 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788416602099 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788416602100 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788416602102 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788416602176 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416602782 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788416603054 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788416603331 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416603332 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788416604198 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788416609582 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788416609582 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788416609824 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788416609824 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788416609824 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416609826 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788416610933 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788416610967 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788416611326 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788416611326 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788416611973 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416614701 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1377 " "Peak virtual memory: 1377 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416615516 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:23:35 2026 " "Processing ended: Thu Sep 3 16:23:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416615516 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416615516 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416615516 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788416615516 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788416617086 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416617086 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:23:36 2026 " "Processing started: Thu Sep 3 16:23:36 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416617086 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788416617086 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788416617086 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788416617741 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788416621997 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416622156 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:23:42 2026 " "Processing ended: Thu Sep 3 16:23:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416622156 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416622156 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416622156 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788416622156 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788416622914 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788416623632 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416623633 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:23:43 2026 " "Processing started: Thu Sep 3 16:23:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416623633 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416623633 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416623633 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788416623690 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788416624157 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788416624157 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416624232 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416624232 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788416624806 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416624807 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416624807 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416624807 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416624808 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416624808 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788416624808 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788416624813 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788416624813 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624814 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624818 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624819 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624819 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624820 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416624821 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788416624823 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788416624861 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788416625968 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416626060 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416626060 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416626061 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416626061 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626062 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626063 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626064 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626064 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626065 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626066 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788416626067 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788416626320 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788416626938 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416626977 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416626977 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416626977 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416626977 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626978 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626979 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626980 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626981 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416626982 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788416626984 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416627131 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416627132 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416627132 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416627132 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416627133 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416627134 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416627135 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416627136 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416627136 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788416628538 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788416628538 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "772 " "Peak virtual memory: 772 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416628560 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:23:48 2026 " "Processing ended: Thu Sep 3 16:23:48 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416628560 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416628560 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416628560 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788416628560 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788416630094 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416630094 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:23:49 2026 " "Processing started: Thu Sep 3 16:23:49 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416630094 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416630094 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416630094 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788416630831 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788416630888 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416630922 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:23:50 2026 " "Processing ended: Thu Sep 3 16:23:50 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416630922 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416630922 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416630922 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416630922 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416631614 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418238472 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:50:38 2026 " "Processing started: Thu Sep 3 16:50:38 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418238472 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238472 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418238473 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418238798 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418238799 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418248175 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418248175 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418248310 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418248991 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418249329 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418249329 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418249357 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418249357 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418249357 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:50:49 2026 " "Processing ended: Thu Sep 3 16:50:49 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418249362 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418249362 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1788418250890 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:50:50 2026 " "Processing started: Thu Sep 3 16:50:50 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418250891 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_fit --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1788418250891 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1788418250948 ""} +{ "Info" "0" "" "Project = q1" { } { } 0 0 "Project = q1" 0 0 "Fitter" 0 0 1788418250949 ""} +{ "Info" "0" "" "Revision = seven_seg" { } { } 0 0 "Revision = seven_seg" 0 0 "Fitter" 0 0 1788418250949 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418251145 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418251145 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418251150 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418251234 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418251659 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418251690 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418251743 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418258575 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258594 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418258596 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258596 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418258597 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418258597 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418258597 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418258597 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418258597 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418258598 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418258598 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418258614 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418264548 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418264548 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418264549 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418264549 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418264550 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418264550 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418264550 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418264553 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418264639 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265244 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418265528 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418265879 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418265879 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418266738 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418272208 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418272208 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418272439 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418272439 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418272442 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418273557 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273604 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418273960 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418273961 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418274597 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418277269 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1379 " "Peak virtual memory: 1379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:18 2026 " "Processing ended: Thu Sep 3 16:51:18 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418278082 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418278082 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1788418279693 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:19 2026 " "Processing started: Thu Sep 3 16:51:19 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418279694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418279694 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418280347 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418284575 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:24 2026 " "Processing ended: Thu Sep 3 16:51:24 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418284739 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418284739 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1788418285414 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1788418286132 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:25 2026 " "Processing started: Thu Sep 3 16:51:25 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418286132 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286132 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418286133 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418286190 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418286659 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418286659 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286734 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418286735 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418287305 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418287305 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418287306 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418287306 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418287307 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418287311 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418287312 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287313 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287316 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287317 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287318 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418287319 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418287321 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418287359 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418288432 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418288531 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418288531 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288532 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288534 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288535 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418288536 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418288538 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418288787 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418289393 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289431 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289432 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289433 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289434 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289435 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289436 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418289438 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418289582 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418289583 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289585 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289586 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289587 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289588 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418289589 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418291002 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:31 2026 " "Processing ended: Thu Sep 3 16:51:31 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418291025 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418291025 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1788418292644 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:51:32 2026 " "Processing started: Thu Sep 3 16:51:32 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418292645 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418292645 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418293402 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418293464 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:51:33 2026 " "Processing ended: Thu Sep 3 16:51:33 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418293508 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418293508 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418294224 ""} diff --git a/Quartus/A1_Q1/db/q1.quiproj.6836.rdr.flock b/Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock similarity index 100% rename from Quartus/A1_Q1/db/q1.quiproj.6836.rdr.flock rename to Quartus/A1_Q1/db/q1.quiproj.10677.rdr.flock diff --git a/Quartus/A1_Q1/db/seven_seg.(0).cnf.cdb b/Quartus/A1_Q1/db/seven_seg.(0).cnf.cdb index 9820a6f..e64a0cd 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.(0).cnf.cdb and b/Quartus/A1_Q1/db/seven_seg.(0).cnf.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb b/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb index b48bcb8..d2e5801 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb and b/Quartus/A1_Q1/db/seven_seg.(0).cnf.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.asm.qmsg b/Quartus/A1_Q1/db/seven_seg.asm.qmsg index 3fa9445..2719942 100644 --- a/Quartus/A1_Q1/db/seven_seg.asm.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788416926283 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416926283 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:28:46 2026 " "Processing started: Thu Sep 3 16:28:46 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416926283 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788416926283 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788416926284 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788416926945 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788416931212 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "521 " "Peak virtual memory: 521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416931367 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:28:51 2026 " "Processing ended: Thu Sep 3 16:28:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416931367 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416931367 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416931367 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788416931367 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418657395 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:37 2026 " "Processing started: Thu Sep 3 16:57:37 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418657395 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1788418657395 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1788418658046 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1788418662314 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:42 2026 " "Processing ended: Thu Sep 3 16:57:42 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418662476 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1788418662476 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.asm.rdb b/Quartus/A1_Q1/db/seven_seg.asm.rdb index e8e2d43..6ea3680 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.asm.rdb and b/Quartus/A1_Q1/db/seven_seg.asm.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.bpm b/Quartus/A1_Q1/db/seven_seg.cmp.bpm index f1fe1e0..82a5011 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.bpm and b/Quartus/A1_Q1/db/seven_seg.cmp.bpm differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.cdb b/Quartus/A1_Q1/db/seven_seg.cmp.cdb index d9b5c81..3d63b43 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.cdb and b/Quartus/A1_Q1/db/seven_seg.cmp.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.hdb b/Quartus/A1_Q1/db/seven_seg.cmp.hdb index a41efb8..f2a262e 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.hdb and b/Quartus/A1_Q1/db/seven_seg.cmp.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.idb b/Quartus/A1_Q1/db/seven_seg.cmp.idb index 12ea329..097f07e 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.idb and b/Quartus/A1_Q1/db/seven_seg.cmp.idb differ diff --git a/Quartus/A1_Q1/db/seven_seg.cmp.rdb b/Quartus/A1_Q1/db/seven_seg.cmp.rdb index bf504cc..742cedc 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.cmp.rdb and b/Quartus/A1_Q1/db/seven_seg.cmp.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.db_info b/Quartus/A1_Q1/db/seven_seg.db_info index 234e735..29cc534 100644 --- a/Quartus/A1_Q1/db/seven_seg.db_info +++ b/Quartus/A1_Q1/db/seven_seg.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Version_Index = 604268800 -Creation_Time = Thu Sep 3 16:08:43 2026 +Creation_Time = Thu Sep 3 19:21:31 2026 diff --git a/Quartus/A1_Q1/db/seven_seg.eda.qmsg b/Quartus/A1_Q1/db/seven_seg.eda.qmsg index df79128..6108a84 100644 --- a/Quartus/A1_Q1/db/seven_seg.eda.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788416939593 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416939594 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:28:59 2026 " "Processing started: Thu Sep 3 16:28:59 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416939594 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416939594 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416939594 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788416940335 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788416940390 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416940427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:29:00 2026 " "Processing ended: Thu Sep 3 16:29:00 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416940427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416940427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416940427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788416940427 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418670701 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:50 2026 " "Processing started: Thu Sep 3 16:57:50 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418670701 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670701 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg " "Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418670702 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1788418671436 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "seven_seg.svo /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/ simulation " "Generated file seven_seg.svo in folder \"/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1788418671488 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "658 " "Peak virtual memory: 658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:51 2026 " "Processing ended: Thu Sep 3 16:57:51 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418671527 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1788418671527 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.fit.qmsg b/Quartus/A1_Q1/db/seven_seg.fit.qmsg index 474d257..c41a542 100644 --- a/Quartus/A1_Q1/db/seven_seg.fit.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.fit.qmsg @@ -1,43 +1,43 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788416898006 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788416898006 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788416898011 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788416898082 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788416898082 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788416898496 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788416898523 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788416898571 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788416905333 ""} -{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416905352 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788416905354 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788416905355 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788416905355 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788416905355 ""} -{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416905371 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788416911196 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788416911196 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788416911197 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788416911197 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788416911198 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788416911198 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788416911198 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788416911201 ""} -{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788416911274 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416911869 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788416912145 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788416912419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416912419 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788416913348 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X57_Y0 X68_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11"} { { 12 { 0 ""} 57 0 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788416918784 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788416918784 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788416919024 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788416919024 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788416919024 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416919026 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788416920110 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788416920145 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788416920500 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788416920500 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788416921216 ""} -{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788416923934 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1387 " "Peak virtual memory: 1387 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416924741 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:28:44 2026 " "Processing ended: Thu Sep 3 16:28:44 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416924741 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416924741 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416924741 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788416924741 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1788418628799 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1788418628800 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "seven_seg 5CGXFC5C6F27C7 " "Selected device 5CGXFC5C6F27C7 for design \"seven_seg\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1788418628804 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1788418628870 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1788418629270 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1788418629302 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1788418629350 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1788418636105 ""} +{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636123 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1788418636125 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636125 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1788418636126 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1788418636126 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1788418636126 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1788418636126 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1788418636126 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1788418636126 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1788418636126 ""} +{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:07 " "Fitter preparation operations ending: elapsed time is 00:00:07" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418636143 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1788418642018 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1788418642018 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1788418642019 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1788418642019 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1788418642020 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1788418642020 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1788418642021 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1788418642023 ""} +{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1788418642102 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418642704 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1788418643216 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1788418643462 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418643462 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1788418644424 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1788418649870 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1788418649870 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1788418650096 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1788418650096 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418650098 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.08 " "Total time spent on timing analysis during the Fitter is 0.08 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1788418651194 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651229 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418651579 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1788418651580 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1788418652299 ""} +{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1788418655001 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1384 " "Peak virtual memory: 1384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:35 2026 " "Processing ended: Thu Sep 3 16:57:35 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418655800 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1788418655800 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.hier_info b/Quartus/A1_Q1/db/seven_seg.hier_info index 23cea17..ed04d1b 100644 --- a/Quartus/A1_Q1/db/seven_seg.hier_info +++ b/Quartus/A1_Q1/db/seven_seg.hier_info @@ -1,32 +1,32 @@ |seven_seg +num[0] => Decoder0.IN3 num[0] => Mux0.IN19 num[0] => Mux1.IN19 num[0] => Mux2.IN19 num[0] => Mux3.IN19 num[0] => Mux4.IN19 num[0] => Mux5.IN19 -num[0] => Decoder0.IN3 +num[1] => Decoder0.IN2 num[1] => Mux0.IN18 num[1] => Mux1.IN18 num[1] => Mux2.IN18 num[1] => Mux3.IN18 num[1] => Mux4.IN18 num[1] => Mux5.IN18 -num[1] => Decoder0.IN2 +num[2] => Decoder0.IN1 num[2] => Mux0.IN17 num[2] => Mux1.IN17 num[2] => Mux2.IN17 num[2] => Mux3.IN17 num[2] => Mux4.IN17 num[2] => Mux5.IN17 -num[2] => Decoder0.IN1 +num[3] => Decoder0.IN0 num[3] => Mux0.IN16 num[3] => Mux1.IN16 num[3] => Mux2.IN16 num[3] => Mux3.IN16 num[3] => Mux4.IN16 num[3] => Mux5.IN16 -num[3] => Decoder0.IN0 rbi_inv[0] => Mux0.IN15 rbi_inv[0] => Mux1.IN15 rbi_inv[0] => Mux2.IN15 @@ -35,12 +35,12 @@ rbi_inv[0] => Mux4.IN15 rbi_inv[0] => Mux5.IN15 rbi_inv[0] => segments.DATAB segments[0] <= segments.DB_MAX_OUTPUT_PORT_TYPE -segments[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -segments[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE -segments[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE -segments[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE -segments[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE -segments[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE -segments[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE +segments[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE +segments[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE +segments[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE +segments[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE +segments[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE +segments[7] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE diff --git a/Quartus/A1_Q1/db/seven_seg.hif b/Quartus/A1_Q1/db/seven_seg.hif index 22244c1..a0766cd 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.hif and b/Quartus/A1_Q1/db/seven_seg.hif differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.bpm b/Quartus/A1_Q1/db/seven_seg.map.bpm index d26ba8d..66b6e2b 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.bpm and b/Quartus/A1_Q1/db/seven_seg.map.bpm differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.cdb b/Quartus/A1_Q1/db/seven_seg.map.cdb index 34aafe7..58f3103 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.cdb and b/Quartus/A1_Q1/db/seven_seg.map.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.hdb b/Quartus/A1_Q1/db/seven_seg.map.hdb index 499a62c..21f45f2 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.hdb and b/Quartus/A1_Q1/db/seven_seg.map.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map.qmsg b/Quartus/A1_Q1/db/seven_seg.map.qmsg index 6c2e2ef..4493d3b 100644 --- a/Quartus/A1_Q1/db/seven_seg.map.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.map.qmsg @@ -1,11 +1,11 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788416885506 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416885506 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:28:05 2026 " "Processing started: Thu Sep 3 16:28:05 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416885506 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416885506 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416885507 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788416885835 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788416885835 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788416895121 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416895121 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788416895251 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788416895965 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788416896307 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788416896307 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788416896335 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788416896335 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788416896335 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788416896335 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416896341 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:28:16 2026 " "Processing ended: Thu Sep 3 16:28:16 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416896341 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416896341 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416896341 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788416896341 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418615772 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:56:55 2026 " "Processing started: Thu Sep 3 16:56:55 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418615772 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615772 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg " "Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418615773 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1788418616096 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1788418616097 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seven_seg.sv 1 1 " "Found 1 design units, including 1 entities, in source file seven_seg.sv" { { "Info" "ISGN_ENTITY_NAME" "1 seven_seg " "Found entity 1: seven_seg" { } { { "seven_seg.sv" "" { Text "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/seven_seg.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1788418625920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418625920 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "seven_seg " "Elaborating entity \"seven_seg\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1788418626051 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1788418626737 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1788418627068 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1788418627068 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1788418627106 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1788418627106 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1788418627106 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "436 " "Peak virtual memory: 436 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:07 2026 " "Processing ended: Thu Sep 3 16:57:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418627114 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1788418627114 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.map.rdb b/Quartus/A1_Q1/db/seven_seg.map.rdb index 1f4c66c..c479cbe 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map.rdb and b/Quartus/A1_Q1/db/seven_seg.map.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map_bb.cdb b/Quartus/A1_Q1/db/seven_seg.map_bb.cdb index 6b43dad..a7702af 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map_bb.cdb and b/Quartus/A1_Q1/db/seven_seg.map_bb.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.map_bb.hdb b/Quartus/A1_Q1/db/seven_seg.map_bb.hdb index fa954cb..bc3c454 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.map_bb.hdb and b/Quartus/A1_Q1/db/seven_seg.map_bb.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.pplq.rdb b/Quartus/A1_Q1/db/seven_seg.pplq.rdb index 46c284e..e1f255e 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.pplq.rdb and b/Quartus/A1_Q1/db/seven_seg.pplq.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.pre_map.hdb b/Quartus/A1_Q1/db/seven_seg.pre_map.hdb index 8c2b32e..eeae3d2 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.pre_map.hdb and b/Quartus/A1_Q1/db/seven_seg.pre_map.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.routing.rdb b/Quartus/A1_Q1/db/seven_seg.routing.rdb index a34eac0..3aed6b5 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.routing.rdb and b/Quartus/A1_Q1/db/seven_seg.routing.rdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.rtlv.hdb b/Quartus/A1_Q1/db/seven_seg.rtlv.hdb index 46d8ce8..6849aa1 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.rtlv.hdb and b/Quartus/A1_Q1/db/seven_seg.rtlv.hdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.rtlv_sg.cdb b/Quartus/A1_Q1/db/seven_seg.rtlv_sg.cdb index 9b3313d..928b277 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.rtlv_sg.cdb and b/Quartus/A1_Q1/db/seven_seg.rtlv_sg.cdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.sta.qmsg b/Quartus/A1_Q1/db/seven_seg.sta.qmsg index 50815be..cb3222b 100644 --- a/Quartus/A1_Q1/db/seven_seg.sta.qmsg +++ b/Quartus/A1_Q1/db/seven_seg.sta.qmsg @@ -1,61 +1,61 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788416932830 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788416932831 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:28:52 2026 " "Processing started: Thu Sep 3 16:28:52 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788416932831 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416932831 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416932831 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788416932887 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788416933360 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788416933360 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416933434 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416933434 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788416934001 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416934001 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416934002 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416934002 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788416934002 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416934003 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788416934003 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788416934007 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788416934008 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934009 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934013 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934014 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934015 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934015 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416934016 ""} -{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788416934018 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788416934056 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788416935348 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416935450 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416935450 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416935450 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416935450 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935451 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935452 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935453 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935454 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935455 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416935455 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788416935457 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788416935719 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788416936416 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416936454 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416936454 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416936455 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416936455 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936456 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936457 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936458 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936459 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936459 ""} -{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788416936461 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788416936612 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788416936612 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788416936613 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788416936613 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936614 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936615 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936616 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936617 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788416936617 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788416938015 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788416938016 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "792 " "Peak virtual memory: 792 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788416938038 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:28:58 2026 " "Processing ended: Thu Sep 3 16:28:58 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788416938038 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788416938038 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788416938038 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788416938038 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1788418663922 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 3 16:57:43 2026 " "Processing started: Thu Sep 3 16:57:43 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1788418663923 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta q1 -c seven_seg " "Command: quartus_sta q1 -c seven_seg" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418663923 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1788418663978 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1788418664459 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1788418664459 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418664532 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "seven_seg.sdc " "Synopsys Design Constraints File file not found: 'seven_seg.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1788418665100 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418665100 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418665101 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1788418665102 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1788418665106 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418665107 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665108 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665111 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665112 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665113 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418665114 ""} +{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418665117 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418665154 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418666438 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418666534 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418666535 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666535 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666537 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666538 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666539 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418666540 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1788418666542 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1788418666803 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1788418667501 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667545 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667546 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667547 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667548 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667549 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667550 ""} +{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1788418667552 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1788418667701 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1788418667702 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667703 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667704 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667705 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1788418667706 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1788418669108 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "780 " "Peak virtual memory: 780 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 3 16:57:49 2026 " "Processing ended: Thu Sep 3 16:57:49 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1788418669130 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1788418669130 ""} diff --git a/Quartus/A1_Q1/db/seven_seg.sta_cmp.7_H6_slow_1100mv_85c.tdb b/Quartus/A1_Q1/db/seven_seg.sta_cmp.7_H6_slow_1100mv_85c.tdb index 222f88b..4bac463 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.sta_cmp.7_H6_slow_1100mv_85c.tdb and b/Quartus/A1_Q1/db/seven_seg.sta_cmp.7_H6_slow_1100mv_85c.tdb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb index 173adc7..5aec916 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb index 97435fd..7703ee2 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fast_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_0c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_0c.ddb index d5042d8..e784d75 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_0c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_85c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_85c.ddb index 5ab62d8..4653189 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_85c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.fastest_slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb index 7d01a58..d24c30c 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_0c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb index 586270d..db35da7 100644 Binary files a/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb and b/Quartus/A1_Q1/db/seven_seg.tiscmp.slow_1100mv_85c.ddb differ diff --git a/Quartus/A1_Q1/db/seven_seg.tmw_info b/Quartus/A1_Q1/db/seven_seg.tmw_info index f50070b..a784bf2 100644 --- a/Quartus/A1_Q1/db/seven_seg.tmw_info +++ b/Quartus/A1_Q1/db/seven_seg.tmw_info @@ -1,5 +1,5 @@ -start_full_compilation:s:00:00:57 -start_analysis_synthesis:s:00:00:12-start_full_compilation +start_full_compilation:s:00:00:58 +start_analysis_synthesis:s:00:00:13-start_full_compilation start_analysis_elaboration:s-start_full_compilation start_fitter:s:00:00:29-start_full_compilation start_assembler:s:00:00:07-start_full_compilation diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb index 066b1d9..dfaed70 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb index 36c9868..da5f897 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb index c0d386b..db5650c 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hbdb.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb index b4e5715..d7b6841 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.rcfdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.rcfdb index 283bd16..ec7c577 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.rcfdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.cmp.rcfdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb index c11531f..fb0de4d 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi index 75169ed..2e48f00 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.dpi differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb index 6af625e..368fd17 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.cdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb index b3a077a..f64424f 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hbdb.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb index adf229a..3d67a7d 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.root_partition.map.hdb differ diff --git a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb index 68a5474..71f0934 100644 Binary files a/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb and b/Quartus/A1_Q1/incremental_db/compiled_partitions/seven_seg.rrp.hdb differ diff --git a/Quartus/A1_Q1/output_files/seven_seg.asm.rpt b/Quartus/A1_Q1/output_files/seven_seg.asm.rpt index 3f1a56f..7a7edcc 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.asm.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.asm.rpt @@ -1,5 +1,5 @@ Assembler report for seven_seg -Thu Sep 3 16:28:51 2026 +Thu Sep 3 16:57:42 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -38,7 +38,7 @@ on the Quartus Prime software download page. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Sep 3 16:28:51 2026 ; +; Assembler Status ; Successful - Thu Sep 3 16:57:42 2026 ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; ; Family ; Cyclone V ; @@ -67,8 +67,8 @@ on the Quartus Prime software download page. +----------------+------------------------+ ; Option ; Setting ; +----------------+------------------------+ -; JTAG usercode ; 0x00781BE2 ; -; Checksum ; 0x00781BE2 ; +; JTAG usercode ; 0x00781CB4 ; +; Checksum ; 0x00781CB4 ; +----------------+------------------------+ @@ -78,13 +78,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:28:46 2026 + Info: Processing started: Thu Sep 3 16:57:37 2026 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 521 megabytes - Info: Processing ended: Thu Sep 3 16:28:51 2026 + Info: Peak virtual memory: 525 megabytes + Info: Processing ended: Thu Sep 3 16:57:42 2026 Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q1/output_files/seven_seg.done b/Quartus/A1_Q1/output_files/seven_seg.done index 3705008..69bf9c6 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.done +++ b/Quartus/A1_Q1/output_files/seven_seg.done @@ -1 +1 @@ -Thu Sep 3 16:29:01 2026 +Thu Sep 3 16:57:52 2026 diff --git a/Quartus/A1_Q1/output_files/seven_seg.eda.rpt b/Quartus/A1_Q1/output_files/seven_seg.eda.rpt index 5c6c586..fe6fc98 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.eda.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for seven_seg -Thu Sep 3 16:29:00 2026 +Thu Sep 3 16:57:51 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -37,7 +37,7 @@ on the Quartus Prime software download page. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Thu Sep 3 16:29:00 2026 ; +; EDA Netlist Writer Status ; Successful - Thu Sep 3 16:57:51 2026 ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; ; Family ; Cyclone V ; @@ -81,13 +81,13 @@ on the Quartus Prime software download page. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:28:59 2026 + Info: Processing started: Thu Sep 3 16:57:50 2026 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file seven_seg.svo in folder "/home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartus/A1_Q1/simulation/questa/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 658 megabytes - Info: Processing ended: Thu Sep 3 16:29:00 2026 + Info: Processing ended: Thu Sep 3 16:57:51 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/Quartus/A1_Q1/output_files/seven_seg.fit.rpt b/Quartus/A1_Q1/output_files/seven_seg.fit.rpt index 6912b72..95e9a7e 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.fit.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.fit.rpt @@ -1,5 +1,5 @@ Fitter report for seven_seg -Thu Sep 3 16:28:44 2026 +Thu Sep 3 16:57:35 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -57,7 +57,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Sep 3 16:28:44 2026 ; +; Fitter Status ; Successful - Thu Sep 3 16:57:35 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -271,7 +271,7 @@ The pin-out file can be found in /home/oliver/Documents/FPGA_Dev/FPGA_Uni/Quartu ; Impedance control blocks ; 0 / 3 ; 0 % ; ; Hard Memory Controllers ; 0 / 2 ; 0 % ; ; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ; ; -; Peak interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.1% ; ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.2% / 0.1% ; ; ; Maximum fan-out ; 8 ; ; ; Highest non-global fan-out ; 8 ; ; ; Total fan-out ; 60 ; ; @@ -1138,7 +1138,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; segments[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; segments[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; ; num[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -; rbi_inv[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; +; rbi_inv[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; ; num[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; num[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; ; num[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; @@ -1152,48 +1152,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------------+-------------------+---------+ ; num[0] ; ; ; ; - segments~0 ; 0 ; 0 ; -; - WideOr0~0 ; 0 ; 0 ; ; - Mux5~0 ; 0 ; 0 ; ; - Mux4~0 ; 0 ; 0 ; ; - Mux3~0 ; 0 ; 0 ; ; - Mux2~0 ; 0 ; 0 ; ; - Mux1~0 ; 0 ; 0 ; ; - Mux0~0 ; 0 ; 0 ; +; - WideOr0~0 ; 0 ; 0 ; ; rbi_inv[0] ; ; ; -; - segments~0 ; 1 ; 0 ; -; - Mux5~0 ; 1 ; 0 ; -; - Mux4~0 ; 1 ; 0 ; -; - Mux3~0 ; 1 ; 0 ; -; - Mux2~0 ; 1 ; 0 ; -; - Mux1~0 ; 1 ; 0 ; -; - Mux0~0 ; 1 ; 0 ; +; - segments~0 ; 0 ; 0 ; +; - Mux5~0 ; 0 ; 0 ; +; - Mux4~0 ; 0 ; 0 ; +; - Mux3~0 ; 0 ; 0 ; +; - Mux2~0 ; 0 ; 0 ; +; - Mux1~0 ; 0 ; 0 ; +; - Mux0~0 ; 0 ; 0 ; ; num[3] ; ; ; ; - segments~0 ; 1 ; 0 ; -; - WideOr0~0 ; 1 ; 0 ; ; - Mux5~0 ; 1 ; 0 ; ; - Mux4~0 ; 1 ; 0 ; ; - Mux3~0 ; 1 ; 0 ; ; - Mux2~0 ; 1 ; 0 ; ; - Mux1~0 ; 1 ; 0 ; ; - Mux0~0 ; 1 ; 0 ; +; - WideOr0~0 ; 1 ; 0 ; ; num[1] ; ; ; ; - segments~0 ; 1 ; 0 ; -; - WideOr0~0 ; 1 ; 0 ; ; - Mux5~0 ; 1 ; 0 ; ; - Mux4~0 ; 1 ; 0 ; ; - Mux3~0 ; 1 ; 0 ; ; - Mux2~0 ; 1 ; 0 ; ; - Mux1~0 ; 1 ; 0 ; ; - Mux0~0 ; 1 ; 0 ; +; - WideOr0~0 ; 1 ; 0 ; ; num[2] ; ; ; ; - segments~0 ; 1 ; 0 ; -; - WideOr0~0 ; 1 ; 0 ; ; - Mux5~0 ; 1 ; 0 ; ; - Mux4~0 ; 1 ; 0 ; ; - Mux3~0 ; 1 ; 0 ; ; - Mux2~0 ; 1 ; 0 ; ; - Mux1~0 ; 1 ; 0 ; ; - Mux0~0 ; 1 ; 0 ; +; - WideOr0~0 ; 1 ; 0 ; +---------------------+-------------------+---------+ @@ -1204,8 +1204,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------+------------------------+ ; Block interconnects ; 13 / 217,884 ( < 1 % ) ; ; C12 interconnects ; 0 / 10,080 ( 0 % ) ; -; C2 interconnects ; 8 / 87,208 ( < 1 % ) ; -; C4 interconnects ; 19 / 41,360 ( < 1 % ) ; +; C2 interconnects ; 10 / 87,208 ( < 1 % ) ; +; C4 interconnects ; 17 / 41,360 ( < 1 % ) ; ; DQS bus muxes ; 0 / 21 ( 0 % ) ; ; DQS-18 I/O buses ; 0 / 21 ( 0 % ) ; ; DQS-9 I/O buses ; 0 / 21 ( 0 % ) ; @@ -1216,8 +1216,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Quadrant clocks ; 0 / 88 ( 0 % ) ; ; R14 interconnects ; 10 / 9,228 ( < 1 % ) ; ; R14/C12 interconnect drivers ; 10 / 15,096 ( < 1 % ) ; -; R3 interconnects ; 11 / 94,896 ( < 1 % ) ; -; R6 interconnects ; 20 / 194,640 ( < 1 % ) ; +; R3 interconnects ; 13 / 94,896 ( < 1 % ) ; +; R6 interconnects ; 19 / 194,640 ( < 1 % ) ; ; Spine clocks ; 0 / 180 ( 0 % ) ; ; Wire stub REs ; 0 / 11,606 ( 0 % ) ; +------------------------------+------------------------+ @@ -1373,7 +1373,7 @@ Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X57_Y0 to location X68_Y11 + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped @@ -1383,10 +1383,10 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03 +Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04 Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 1387 megabytes - Info: Processing ended: Thu Sep 3 16:28:44 2026 + Info: Peak virtual memory: 1384 megabytes + Info: Processing ended: Thu Sep 3 16:57:35 2026 Info: Elapsed time: 00:00:27 Info: Total CPU time (on all processors): 00:00:39 diff --git a/Quartus/A1_Q1/output_files/seven_seg.fit.summary b/Quartus/A1_Q1/output_files/seven_seg.fit.summary index 435705a..43a8a6e 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.fit.summary +++ b/Quartus/A1_Q1/output_files/seven_seg.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Thu Sep 3 16:28:44 2026 +Fitter Status : Successful - Thu Sep 3 16:57:35 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : seven_seg Top-level Entity Name : seven_seg diff --git a/Quartus/A1_Q1/output_files/seven_seg.flow.rpt b/Quartus/A1_Q1/output_files/seven_seg.flow.rpt index 1e880dd..1c1558d 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.flow.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.flow.rpt @@ -1,5 +1,5 @@ Flow report for seven_seg -Thu Sep 3 16:29:00 2026 +Thu Sep 3 16:57:51 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -41,7 +41,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Sep 3 16:29:00 2026 ; +; Flow Status ; Successful - Thu Sep 3 16:57:51 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -68,7 +68,7 @@ on the Quartus Prime software download page. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/03/2026 16:28:05 ; +; Start date & time ; 09/03/2026 16:56:55 ; ; Main task ; Compilation ; ; Revision Name ; seven_seg ; +-------------------+---------------------+ @@ -79,7 +79,7 @@ on the Quartus Prime software download page. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 55629860311554.178841688507944 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 55629860311554.178841861509729 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ on the Quartus Prime software download page. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:25 ; -; Fitter ; 00:00:27 ; 1.0 ; 1387 MB ; 00:00:38 ; -; Assembler ; 00:00:05 ; 1.0 ; 521 MB ; 00:00:05 ; -; Timing Analyzer ; 00:00:06 ; 1.0 ; 792 MB ; 00:00:05 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 419 MB ; 00:00:27 ; +; Fitter ; 00:00:27 ; 1.0 ; 1384 MB ; 00:00:38 ; +; Assembler ; 00:00:05 ; 1.0 ; 525 MB ; 00:00:05 ; +; Timing Analyzer ; 00:00:06 ; 1.0 ; 780 MB ; 00:00:05 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 658 MB ; 00:00:01 ; -; Total ; 00:00:50 ; -- ; -- ; 00:01:14 ; +; Total ; 00:00:50 ; -- ; -- ; 00:01:16 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/Quartus/A1_Q1/output_files/seven_seg.map.rpt b/Quartus/A1_Q1/output_files/seven_seg.map.rpt index 0f37381..b10d946 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.map.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for seven_seg -Thu Sep 3 16:28:16 2026 +Thu Sep 3 16:57:07 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -44,7 +44,7 @@ on the Quartus Prime software download page. +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +---------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Sep 3 16:28:16 2026 ; +; Analysis & Synthesis Status ; Successful - Thu Sep 3 16:57:07 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; seven_seg ; ; Top-level Entity Name ; seven_seg ; @@ -233,7 +233,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ -; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |seven_seg|Mux5 ; +; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |seven_seg|Mux3 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -269,7 +269,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:28:05 2026 + Info: Processing started: Thu Sep 3 16:56:55 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off q1 -c seven_seg Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected @@ -285,8 +285,8 @@ Info (21057): Implemented 21 device resources after synthesis - the final resour Info (21061): Implemented 8 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning Info: Peak virtual memory: 436 megabytes - Info: Processing ended: Thu Sep 3 16:28:16 2026 - Info: Elapsed time: 00:00:11 - Info: Total CPU time (on all processors): 00:00:25 + Info: Processing ended: Thu Sep 3 16:57:07 2026 + Info: Elapsed time: 00:00:12 + Info: Total CPU time (on all processors): 00:00:27 diff --git a/Quartus/A1_Q1/output_files/seven_seg.map.summary b/Quartus/A1_Q1/output_files/seven_seg.map.summary index d2e35c9..8165f2a 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.map.summary +++ b/Quartus/A1_Q1/output_files/seven_seg.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Thu Sep 3 16:28:16 2026 +Analysis & Synthesis Status : Successful - Thu Sep 3 16:57:07 2026 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Revision Name : seven_seg Top-level Entity Name : seven_seg diff --git a/Quartus/A1_Q1/output_files/seven_seg.sof b/Quartus/A1_Q1/output_files/seven_seg.sof index d03d07c..2c3ddcd 100644 Binary files a/Quartus/A1_Q1/output_files/seven_seg.sof and b/Quartus/A1_Q1/output_files/seven_seg.sof differ diff --git a/Quartus/A1_Q1/output_files/seven_seg.sta.rpt b/Quartus/A1_Q1/output_files/seven_seg.sta.rpt index 55654e6..d1e38f0 100644 --- a/Quartus/A1_Q1/output_files/seven_seg.sta.rpt +++ b/Quartus/A1_Q1/output_files/seven_seg.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for seven_seg -Thu Sep 3 16:28:58 2026 +Thu Sep 3 16:57:49 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition @@ -474,7 +474,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition - Info: Processing started: Thu Sep 3 16:28:52 2026 + Info: Processing started: Thu Sep 3 16:57:43 2026 Info: Command: quartus_sta q1 -c seven_seg Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -534,8 +534,8 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 6 warnings - Info: Peak virtual memory: 792 megabytes - Info: Processing ended: Thu Sep 3 16:28:58 2026 + Info: Peak virtual memory: 780 megabytes + Info: Processing ended: Thu Sep 3 16:57:49 2026 Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:05 diff --git a/Quartus/A1_Q1/seven_seg.qws b/Quartus/A1_Q1/seven_seg.qws deleted file mode 100644 index def0ac6..0000000 Binary files a/Quartus/A1_Q1/seven_seg.qws and /dev/null differ diff --git a/Quartus/A1_Q1/seven_seg.sv b/Quartus/A1_Q1/seven_seg.sv index 413cddd..6f19c81 100644 --- a/Quartus/A1_Q1/seven_seg.sv +++ b/Quartus/A1_Q1/seven_seg.sv @@ -1,22 +1,22 @@ module seven_seg(input logic [3:0] num, input logic [0:0] rbi_inv, output logic [7:0] segments); always_comb begin case (num) - 4'b0000: segments = (rbi_inv) ? ~(8'b11111101) : ~(8'b00000000); - 4'b0001: segments = ~(8'b01100001); - 4'b0010: segments = ~(8'b11011011); - 4'b0011: segments = ~(8'b11110011); - 4'b0100: segments = ~(8'b01100111); - 4'b0101: segments = ~(8'b10110111); - 4'b0110: segments = ~(8'b10111111); - 4'b0111: segments = ~(8'b11100001); + 4'b0000: segments = (rbi_inv) ? ~(8'b01111111) : ~(8'b00000000); + 4'b0001: segments = ~(8'b00001101); + 4'b0010: segments = ~(8'b10110111); + 4'b0011: segments = ~(8'b10011111); + 4'b0100: segments = ~(8'b11001101); + 4'b0101: segments = ~(8'b11011011); + 4'b0110: segments = ~(8'b11111011); + 4'b0111: segments = ~(8'b00001111); 4'b1000: segments = ~(8'b11111111); - 4'b1001: segments = ~(8'b11100111); + 4'b1001: segments = ~(8'b11001111); 4'b1010: segments = ~(8'b11101111); - 4'b1011: segments = ~(8'b00111111); - 4'b1100: segments = ~(8'b10011101); - 4'b1101: segments = ~(8'b01111011); - 4'b1110: segments = ~(8'b10011111); - 4'b1111: segments = ~(8'b10001111); + 4'b1011: segments = ~(8'b11111001); + 4'b1100: segments = ~(8'b01110011); + 4'b1101: segments = ~(8'b10111101); + 4'b1110: segments = ~(8'b11110011); + 4'b1111: segments = ~(8'b11100011); default: segments = ~(8'bxxxxxxxx); endcase end diff --git a/Quartus/A1_Q1/simulation/questa/seven_seg.svo b/Quartus/A1_Q1/simulation/questa/seven_seg.svo index ec2d06d..b554d3a 100644 --- a/Quartus/A1_Q1/simulation/questa/seven_seg.svo +++ b/Quartus/A1_Q1/simulation/questa/seven_seg.svo @@ -17,7 +17,7 @@ // PROGRAM "Quartus Prime" // VERSION "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" -// DATE "09/03/2026 16:29:00" +// DATE "09/03/2026 16:57:51" // // Device: Altera 5CGXFC5C6F27C7 Package FBGA672 @@ -65,19 +65,19 @@ tri1 devclrn; tri1 devpor; tri1 devoe; wire \~QUARTUS_CREATED_GND~I_combout ; -wire \num[1]~input_o ; wire \num[2]~input_o ; -wire \num[0]~input_o ; wire \num[3]~input_o ; +wire \num[0]~input_o ; wire \rbi_inv[0]~input_o ; +wire \num[1]~input_o ; wire \segments~0_combout ; -wire \WideOr0~0_combout ; wire \Mux5~0_combout ; wire \Mux4~0_combout ; wire \Mux3~0_combout ; wire \Mux2~0_combout ; wire \Mux1~0_combout ; wire \Mux0~0_combout ; +wire \WideOr0~0_combout ; // Location: IOOBUF_X14_Y61_N53 @@ -98,7 +98,7 @@ defparam \segments[0]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X66_Y0_N2 cyclonev_io_obuf \segments[1]~output ( - .i(!\WideOr0~0_combout ), + .i(\Mux5~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -114,7 +114,7 @@ defparam \segments[1]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X64_Y0_N2 cyclonev_io_obuf \segments[2]~output ( - .i(\Mux5~0_combout ), + .i(\Mux4~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -130,7 +130,7 @@ defparam \segments[2]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X64_Y0_N19 cyclonev_io_obuf \segments[3]~output ( - .i(\Mux4~0_combout ), + .i(\Mux3~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -146,7 +146,7 @@ defparam \segments[3]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X66_Y0_N19 cyclonev_io_obuf \segments[4]~output ( - .i(\Mux3~0_combout ), + .i(\Mux2~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -162,7 +162,7 @@ defparam \segments[4]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X65_Y0_N2 cyclonev_io_obuf \segments[5]~output ( - .i(\Mux2~0_combout ), + .i(\Mux1~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -178,7 +178,7 @@ defparam \segments[5]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X65_Y0_N19 cyclonev_io_obuf \segments[6]~output ( - .i(\Mux1~0_combout ), + .i(\Mux0~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -194,7 +194,7 @@ defparam \segments[6]~output .shift_series_termination_control = "false"; // Location: IOOBUF_X62_Y0_N42 cyclonev_io_obuf \segments[7]~output ( - .i(\Mux0~0_combout ), + .i(!\WideOr0~0_combout ), .oe(vcc), .dynamicterminationcontrol(gnd), .seriesterminationcontrol(16'b0000000000000000), @@ -208,17 +208,6 @@ defparam \segments[7]~output .open_drain_output = "false"; defparam \segments[7]~output .shift_series_termination_control = "false"; // synopsys translate_on -// Location: IOIBUF_X36_Y0_N52 -cyclonev_io_ibuf \num[1]~input ( - .i(num[1]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\num[1]~input_o )); -// synopsys translate_off -defparam \num[1]~input .bus_hold = "false"; -defparam \num[1]~input .simulate_z_as = "z"; -// synopsys translate_on - // Location: IOIBUF_X34_Y0_N35 cyclonev_io_ibuf \num[2]~input ( .i(num[2]), @@ -230,17 +219,6 @@ defparam \num[2]~input .bus_hold = "false"; defparam \num[2]~input .simulate_z_as = "z"; // synopsys translate_on -// Location: IOIBUF_X14_Y0_N35 -cyclonev_io_ibuf \num[0]~input ( - .i(num[0]), - .ibar(gnd), - .dynamicterminationcontrol(gnd), - .o(\num[0]~input_o )); -// synopsys translate_off -defparam \num[0]~input .bus_hold = "false"; -defparam \num[0]~input .simulate_z_as = "z"; -// synopsys translate_on - // Location: IOIBUF_X14_Y0_N52 cyclonev_io_ibuf \num[3]~input ( .i(num[3]), @@ -252,6 +230,17 @@ defparam \num[3]~input .bus_hold = "false"; defparam \num[3]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X14_Y0_N35 +cyclonev_io_ibuf \num[0]~input ( + .i(num[0]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\num[0]~input_o )); +// synopsys translate_off +defparam \num[0]~input .bus_hold = "false"; +defparam \num[0]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: IOIBUF_X50_Y0_N35 cyclonev_io_ibuf \rbi_inv[0]~input ( .i(rbi_inv[0]), @@ -263,18 +252,29 @@ defparam \rbi_inv[0]~input .bus_hold = "false"; defparam \rbi_inv[0]~input .simulate_z_as = "z"; // synopsys translate_on +// Location: IOIBUF_X36_Y0_N52 +cyclonev_io_ibuf \num[1]~input ( + .i(num[1]), + .ibar(gnd), + .dynamicterminationcontrol(gnd), + .o(\num[1]~input_o )); +// synopsys translate_off +defparam \num[1]~input .bus_hold = "false"; +defparam \num[1]~input .simulate_z_as = "z"; +// synopsys translate_on + // Location: LABCELL_X53_Y1_N30 cyclonev_lcell_comb \segments~0 ( // Equation(s): -// \segments~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o ) ) # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( ((\num[0]~input_o ) # -// (\num[2]~input_o )) # (\num[1]~input_o ) ) ) ) +// \segments~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( ((\num[0]~input_o ) # +// (\num[3]~input_o )) # (\num[2]~input_o ) ) ) ) - .dataa(!\num[1]~input_o ), - .datab(!\num[2]~input_o ), + .dataa(!\num[2]~input_o ), + .datab(!\num[3]~input_o ), .datac(!\num[0]~input_o ), .datad(gnd), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), .datag(gnd), .cin(gnd), .sharein(gnd), @@ -288,17 +288,171 @@ defparam \segments~0 .lut_mask = 64'h7F7FFFFFFFFFFFFF; defparam \segments~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X53_Y1_N9 -cyclonev_lcell_comb \WideOr0~0 ( +// Location: LABCELL_X53_Y1_N39 +cyclonev_lcell_comb \Mux5~0 ( // Equation(s): -// \WideOr0~0_combout = ( \num[3]~input_o & ( \num[1]~input_o ) ) # ( !\num[3]~input_o & ( \num[1]~input_o & ( (!\num[0]~input_o ) # (!\num[2]~input_o ) ) ) ) # ( \num[3]~input_o & ( !\num[1]~input_o & ( (!\num[2]~input_o ) # (\num[0]~input_o ) ) ) ) -// # ( !\num[3]~input_o & ( !\num[1]~input_o & ( \num[2]~input_o ) ) ) +// \Mux5~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (\num[0]~input_o & (\num[3]~input_o & !\num[2]~input_o )) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (\num[0]~input_o & (\num[3]~input_o & !\num[2]~input_o )) ) ) ) # ( +// \rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[0]~input_o & (!\num[3]~input_o & \num[2]~input_o )) # (\num[0]~input_o & (!\num[3]~input_o $ (\num[2]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( !\num[3]~input_o $ +// (((\num[0]~input_o & \num[2]~input_o ))) ) ) ) .dataa(!\num[0]~input_o ), .datab(gnd), - .datac(!\num[2]~input_o ), + .datac(!\num[3]~input_o ), + .datad(!\num[2]~input_o ), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux5~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux5~0 .extended_lut = "off"; +defparam \Mux5~0 .lut_mask = 64'hF0A550A505000500; +defparam \Mux5~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N12 +cyclonev_lcell_comb \Mux4~0 ( +// Equation(s): +// \Mux4~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[0]~input_o & (\num[2]~input_o )) # (\num[0]~input_o & ((\num[3]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[0]~input_o & (\num[2]~input_o )) # +// (\num[0]~input_o & ((\num[3]~input_o ))) ) ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (\num[2]~input_o & (!\num[3]~input_o $ (!\num[0]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[2]~input_o & +// (!\num[3]~input_o & !\num[0]~input_o )) # (\num[2]~input_o & (!\num[3]~input_o $ (!\num[0]~input_o ))) ) ) ) + + .dataa(!\num[2]~input_o ), + .datab(!\num[3]~input_o ), + .datac(!\num[0]~input_o ), .datad(gnd), - .datae(!\num[3]~input_o ), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux4~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux4~0 .extended_lut = "off"; +defparam \Mux4~0 .lut_mask = 64'h9494141453535353; +defparam \Mux4~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N51 +cyclonev_lcell_comb \Mux3~0 ( +// Equation(s): +// \Mux3~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[3]~input_o & (!\num[0]~input_o & !\num[2]~input_o )) # (\num[3]~input_o & ((\num[2]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[3]~input_o & +// (!\num[0]~input_o & !\num[2]~input_o )) # (\num[3]~input_o & ((\num[2]~input_o ))) ) ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[0]~input_o & (\num[3]~input_o & \num[2]~input_o )) ) ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o +// & ( (!\num[0]~input_o & (!\num[3]~input_o $ (\num[2]~input_o ))) ) ) ) + + .dataa(!\num[0]~input_o ), + .datab(gnd), + .datac(!\num[3]~input_o ), + .datad(!\num[2]~input_o ), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux3~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux3~0 .extended_lut = "off"; +defparam \Mux3~0 .lut_mask = 64'hA00A000AA00FA00F; +defparam \Mux3~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N54 +cyclonev_lcell_comb \Mux2~0 ( +// Equation(s): +// \Mux2~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[2]~input_o & (\num[3]~input_o & !\num[0]~input_o )) # (\num[2]~input_o & ((\num[0]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[2]~input_o & +// (\num[3]~input_o & !\num[0]~input_o )) # (\num[2]~input_o & ((\num[0]~input_o ))) ) ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[2]~input_o & ((\num[0]~input_o ))) # (\num[2]~input_o & (!\num[3]~input_o & !\num[0]~input_o )) ) ) ) # +// ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[0]~input_o & ((!\num[3]~input_o ))) # (\num[0]~input_o & (!\num[2]~input_o )) ) ) ) + + .dataa(!\num[2]~input_o ), + .datab(!\num[3]~input_o ), + .datac(!\num[0]~input_o ), + .datad(gnd), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux2~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux2~0 .extended_lut = "off"; +defparam \Mux2~0 .lut_mask = 64'hCACA4A4A25252525; +defparam \Mux2~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N3 +cyclonev_lcell_comb \Mux1~0 ( +// Equation(s): +// \Mux1~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (\num[0]~input_o & !\num[3]~input_o ) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (\num[0]~input_o & !\num[3]~input_o ) ) ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o +// & ( (!\num[2]~input_o & (\num[0]~input_o )) # (\num[2]~input_o & ((!\num[3]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[3]~input_o ) # ((\num[0]~input_o & !\num[2]~input_o )) ) ) ) + + .dataa(!\num[0]~input_o ), + .datab(gnd), + .datac(!\num[3]~input_o ), + .datad(!\num[2]~input_o ), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux1~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux1~0 .extended_lut = "off"; +defparam \Mux1~0 .lut_mask = 64'hF5F055F050505050; +defparam \Mux1~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N6 +cyclonev_lcell_comb \Mux0~0 ( +// Equation(s): +// \Mux0~0_combout = ( \rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[3]~input_o & ((!\num[2]~input_o ) # (\num[0]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( \num[1]~input_o & ( (!\num[3]~input_o & ((!\num[2]~input_o ) # (\num[0]~input_o ))) ) +// ) ) # ( \rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (\num[0]~input_o & (!\num[2]~input_o $ (\num[3]~input_o ))) ) ) ) # ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o & ( (!\num[2]~input_o & (!\num[3]~input_o )) # (\num[2]~input_o & (\num[3]~input_o +// & \num[0]~input_o )) ) ) ) + + .dataa(!\num[2]~input_o ), + .datab(!\num[3]~input_o ), + .datac(!\num[0]~input_o ), + .datad(gnd), + .datae(!\rbi_inv[0]~input_o ), + .dataf(!\num[1]~input_o ), + .datag(gnd), + .cin(gnd), + .sharein(gnd), + .combout(\Mux0~0_combout ), + .sumout(), + .cout(), + .shareout()); +// synopsys translate_off +defparam \Mux0~0 .extended_lut = "off"; +defparam \Mux0~0 .lut_mask = 64'h898909098C8C8C8C; +defparam \Mux0~0 .shared_arith = "off"; +// synopsys translate_on + +// Location: LABCELL_X53_Y1_N45 +cyclonev_lcell_comb \WideOr0~0 ( +// Equation(s): +// \WideOr0~0_combout = ( \num[1]~input_o & ( (!\num[0]~input_o ) # ((!\num[2]~input_o ) # (\num[3]~input_o )) ) ) # ( !\num[1]~input_o & ( (!\num[3]~input_o & ((\num[2]~input_o ))) # (\num[3]~input_o & ((!\num[2]~input_o ) # (\num[0]~input_o ))) ) ) + + .dataa(!\num[0]~input_o ), + .datab(gnd), + .datac(!\num[3]~input_o ), + .datad(!\num[2]~input_o ), + .datae(gnd), .dataf(!\num[1]~input_o ), .datag(gnd), .cin(gnd), @@ -309,163 +463,10 @@ cyclonev_lcell_comb \WideOr0~0 ( .shareout()); // synopsys translate_off defparam \WideOr0~0 .extended_lut = "off"; -defparam \WideOr0~0 .lut_mask = 64'h0F0FF5F5FAFAFFFF; +defparam \WideOr0~0 .lut_mask = 64'h0FF50FF5FFAFFFAF; defparam \WideOr0~0 .shared_arith = "off"; // synopsys translate_on -// Location: LABCELL_X53_Y1_N15 -cyclonev_lcell_comb \Mux5~0 ( -// Equation(s): -// \Mux5~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (\num[0]~input_o & (\num[2]~input_o & !\num[1]~input_o )) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( (!\num[0]~input_o & (!\num[2]~input_o & \num[1]~input_o )) # -// (\num[0]~input_o & ((!\num[2]~input_o ) # (\num[1]~input_o ))) ) ) ) # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (\num[0]~input_o & (\num[2]~input_o & !\num[1]~input_o )) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( -// (!\num[2]~input_o ) # ((\num[0]~input_o & \num[1]~input_o )) ) ) ) - - .dataa(!\num[0]~input_o ), - .datab(gnd), - .datac(!\num[2]~input_o ), - .datad(!\num[1]~input_o ), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux5~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux5~0 .extended_lut = "off"; -defparam \Mux5~0 .lut_mask = 64'hF0F5050050F50500; -defparam \Mux5~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X53_Y1_N18 -cyclonev_lcell_comb \Mux4~0 ( -// Equation(s): -// \Mux4~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (!\num[1]~input_o & (!\num[2]~input_o & \num[0]~input_o )) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( ((!\num[1]~input_o & \num[2]~input_o )) # (\num[0]~input_o ) ) ) ) # -// ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[1]~input_o & (!\num[2]~input_o & \num[0]~input_o )) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[1]~input_o ) # (\num[0]~input_o ) ) ) ) - - .dataa(!\num[1]~input_o ), - .datab(!\num[2]~input_o ), - .datac(!\num[0]~input_o ), - .datad(gnd), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux4~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux4~0 .extended_lut = "off"; -defparam \Mux4~0 .lut_mask = 64'hAFAF08082F2F0808; -defparam \Mux4~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X53_Y1_N27 -cyclonev_lcell_comb \Mux3~0 ( -// Equation(s): -// \Mux3~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (!\num[0]~input_o & (!\num[2]~input_o & \num[1]~input_o )) # (\num[0]~input_o & (!\num[2]~input_o $ (\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( -// (!\num[0]~input_o & (\num[2]~input_o & !\num[1]~input_o )) # (\num[0]~input_o & (!\num[2]~input_o $ (\num[1]~input_o ))) ) ) ) # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[0]~input_o & (!\num[2]~input_o & \num[1]~input_o )) # -// (\num[0]~input_o & (!\num[2]~input_o $ (\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( !\num[1]~input_o $ (((\num[0]~input_o & \num[2]~input_o ))) ) ) ) - - .dataa(!\num[0]~input_o ), - .datab(gnd), - .datac(!\num[2]~input_o ), - .datad(!\num[1]~input_o ), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux3~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux3~0 .extended_lut = "off"; -defparam \Mux3~0 .lut_mask = 64'hFA0550A55A0550A5; -defparam \Mux3~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X53_Y1_N0 -cyclonev_lcell_comb \Mux2~0 ( -// Equation(s): -// \Mux2~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (\num[2]~input_o & ((!\num[0]~input_o ) # (\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( (\num[1]~input_o & (!\num[2]~input_o & !\num[0]~input_o )) ) ) ) -// # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (\num[2]~input_o & ((!\num[0]~input_o ) # (\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[2]~input_o & !\num[0]~input_o ) ) ) ) - - .dataa(!\num[1]~input_o ), - .datab(!\num[2]~input_o ), - .datac(!\num[0]~input_o ), - .datad(gnd), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux2~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux2~0 .extended_lut = "off"; -defparam \Mux2~0 .lut_mask = 64'hC0C0313140403131; -defparam \Mux2~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X53_Y1_N39 -cyclonev_lcell_comb \Mux1~0 ( -// Equation(s): -// \Mux1~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (!\num[0]~input_o & (\num[2]~input_o )) # (\num[0]~input_o & ((\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( (\num[2]~input_o & (!\num[0]~input_o $ -// (!\num[1]~input_o ))) ) ) ) # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[0]~input_o & (\num[2]~input_o )) # (\num[0]~input_o & ((\num[1]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[0]~input_o & -// (!\num[2]~input_o $ (\num[1]~input_o ))) # (\num[0]~input_o & (\num[2]~input_o & !\num[1]~input_o )) ) ) ) - - .dataa(!\num[0]~input_o ), - .datab(gnd), - .datac(!\num[2]~input_o ), - .datad(!\num[1]~input_o ), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux1~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux1~0 .extended_lut = "off"; -defparam \Mux1~0 .lut_mask = 64'hA50A0A5F050A0A5F; -defparam \Mux1~0 .shared_arith = "off"; -// synopsys translate_on - -// Location: LABCELL_X53_Y1_N42 -cyclonev_lcell_comb \Mux0~0 ( -// Equation(s): -// \Mux0~0_combout = ( \num[3]~input_o & ( \rbi_inv[0]~input_o & ( (\num[0]~input_o & (!\num[1]~input_o $ (!\num[2]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( \rbi_inv[0]~input_o & ( (!\num[1]~input_o & (!\num[2]~input_o $ (!\num[0]~input_o ))) ) ) -// ) # ( \num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (\num[0]~input_o & (!\num[1]~input_o $ (!\num[2]~input_o ))) ) ) ) # ( !\num[3]~input_o & ( !\rbi_inv[0]~input_o & ( (!\num[1]~input_o & ((!\num[2]~input_o ) # (!\num[0]~input_o ))) ) ) ) - - .dataa(!\num[1]~input_o ), - .datab(!\num[2]~input_o ), - .datac(!\num[0]~input_o ), - .datad(gnd), - .datae(!\num[3]~input_o ), - .dataf(!\rbi_inv[0]~input_o ), - .datag(gnd), - .cin(gnd), - .sharein(gnd), - .combout(\Mux0~0_combout ), - .sumout(), - .cout(), - .shareout()); -// synopsys translate_off -defparam \Mux0~0 .extended_lut = "off"; -defparam \Mux0~0 .lut_mask = 64'hA8A8060628280606; -defparam \Mux0~0 .shared_arith = "off"; -// synopsys translate_on - // Location: MLABCELL_X55_Y52_N0 cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I ( // Equation(s):