Fixed timing in testbench for branch iteration.

tests/mips.sv

@@ -28,7 +28,7 @@ module mips_tb();
         #2;
         rst = 0;
         #2;
-        
+
         $dumpfile("output.vcd");
 		$dumpvars(0, clk);
 		$dumpvars(1, CPU.REGS);
@@ -82,11 +82,16 @@ module mips_tb();
         `TEST_CHECK(CPU.REGS.regs[21] == $unsigned(CPU.REGS.regs[12]) < $unsigned(CPU.REGS.regs[14]));
         
         // Check loop branching
+        #2;
         for (integer N = 1; N < 11; ++N) begin
             #2;
             `TEST_CHECK(CPU.REGS.regs[8] == 32'(N));
+            
             #2;
             `TEST_CHECK(CPU.REGS.regs[22] == $unsigned(CPU.REGS.regs[8]) < $unsigned(CPU.REGS.regs[13]));
+            if (N < 10)
+                #2;
+            #2;
         end
 
         // Final state check