Merge branch 'main' of ssh://git.rileyk.au:19482/TroubleElectrical/FPGA_Uni

modules/assignment2.sv

@@ -50,6 +50,7 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	logic [2**width-1:0] rt;
 	logic [2**width-1:0] rd;
 	logic [0:0] rd_we;
+	logic [31:0] regs_out [32];
 	
 	instruction_counter #(width) PC (clk, pc_we, pc_addr_write, pc_addr);
 	
@@ -61,12 +62,14 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	control_unit CONTROL_UNIT (instruction[31:26], instruction[5:0],
 		M2R, M2W, B, ALU_FN, ALU_SRC, RDST, RW
 	);
-	
-	register_file #(width, 5) REGS (clk,
-		rd_we, (RDST) ? instruction[15:11] : instruction[20:16],
-		rs, instruction[25:21],
-		rt, instruction[20:16],
-        regs_out 
+
+
+	register_file #(width, 5) REGS (
+		clk, rd_we, 
+		(RDST) ? instruction[15:11] : instruction[20:16], rs,
+		instruction[25:21], rt, 
+		instruction[20:16], rd,
+		regs_out
    );
     // Always use sign-extension
     logic [2**width-1:0] rt_imm;
@@ -80,17 +83,17 @@ module assignment2 #(width=5, ramsz=9, romsz=10) (
 	alu #(width) ALU (ALU_FN, rs, rt_alu, rd_alu, flags[1:0]);
     assign rt_alu = (ALU_SRC) ? (rt_imm) : (rt);
 
-	assign rd_we = RW;
 	assign pc_we = B & flags[2];
-	assign pc_addr_write <= (rt_imm << 2) + pc_addr;
+	assign pc_addr_write = (rt_imm << 2) + pc_addr;
+	assign rd_we = RW;
 	assign rd = (M2R) ? rd_alu : rd_mem;
 
 
 
 	// Temporary Test output
-	assign PC_Reg_Display = 16'hC342;
+	// assign PC_Reg_Display = 16'hC342;
 
-    assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
+   assign PC_Reg_Display = (HID_Hi_Low) ? regs_out[HID_Register][31:16] : regs_out[HID_Register][15:0];
 	
 	seven_seg_4digit display (
 		.num(PC_Reg_Display),